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About austinmags

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  1. austinmags

    Papilio Pro + Logic Wing VGA Pins

    The lesson I took away from this experience is simply not to use the aul option. I don't remember where I learned to use it, but it was allowing me to avoid a slight annoyance with the risk of something much more annoying and harder to diagnose. Also, I'm training myself to read the design report each time (well at least scanning certain parts of it)... imagine that! Next, I need to develop a habit of actually doing a simulation instead of loading up the board and using hard signals to verify and debug it.
  2. austinmags

    Papilio Pro + Logic Wing VGA Pins

    Sorry to spam this thread, but my original project is now working as it should. I now have a red screen! Thanks once more Mike. Boo to typos!
  3. austinmags

    Papilio Pro + Logic Wing VGA Pins

    Nooooooo! :-) So embarrassing with all the bits I just wasted. Thank, you, I'll proceed from here.
  4. austinmags

    Papilio Pro + Logic Wing VGA Pins

    More information. My design properties are: * Family: Spartan6 * Device: XC6SLX9 * Package: TQG144 * Speed: -3 97 is obviously a valid IO pin on that chip. Google is not being very precise with its suggestions when I search for reasons why a constrained pin may be assigned to a different one. Feel like this is a dumb user mistake on my part -- but it's elusive.
  5. austinmags

    Papilio Pro + Logic Wing VGA Pins

    OK, on Mike's suggestion, I've looked more carefully at the design report. I see the problem: -> HSYNC (vga_hsync) is not being assigned pin 97 -- but some other random pin 140. Interesting. I've removed and re-added my constraints file. With no change. Is 97 not valid for the Papilio Pro and specifically for VGA HSYNC on the Logic Wing?
  6. austinmags

    Papilio Pro + Logic Wing VGA Pins

    Hi, thanks Mike for the offer. I've sent a compressed version of my project over to you. Also, after fighting with the online editor, I managed to get an updated and correct version of my diagnostic test. Real puzzler. Hoping one day to generate an actual VGA signal somewhere...
  7. austinmags

    Papilio Pro + Logic Wing VGA Pins

    I was running through the FPGA tutorial by Hamster; hit a hard stop on the VGA chapter. I'm essentially trying to generate a 640x480 60Hz signal which displays a red screen. The monitor consistently reports no signal; I've verified the cable and monitor work independently of the board. My clock appears to be correct; I've used a variety of test configurations to validate I have a 25MHz clock. I'm now measuring signals directly out of the VGA connector on the Logic Wing; the VSYNC signal has been verified, but HSYNC is not produced on the expected VGA connector pin (13) given the Papilio Pro constraints. (I'm measuring using a voltmeter - get 3.3 volts when measuring vsync, 0 when measuring hsync). I'm wondering if either I have a defective test, board, or incorrect constraints for the Papilio Pro / Logic Wing. Any help / guidance would be much appreciated of how to proceed. My diagnostic code: entity VgaDiscoverer isPort (clk : in std_logic;vga_vsync : out std_logic;vga_hsync : out std_logic;switches : in std_logic_vector(7 downto 0));end VgaDiscoverer;architecture Behavioral of VgaDiscoverer isbeginprocess(clk)beginvga_vsync <= switches(0);vga_hsync <= switches(1);end process;end Behavioral; My constraints: NET CLK LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns;NET switches(0) LOC = "P114" | IOSTANDARD=LVTTL;NET switches(1) LOC = "P115" | IOSTANDARD=LVTTL;NET switches(2) LOC = "P116" | IOSTANDARD=LVTTL;NET switches(3) LOC = "P117" | IOSTANDARD=LVTTL;NET switches(4) LOC = "P118" | IOSTANDARD=LVTTL;NET switches(5) LOC = "P119" | IOSTANDARD=LVTTL;NET switches(6) LOC = "P120" | IOSTANDARD=LVTTL;NET switches(7) LOC = "P121" | IOSTANDARD=LVTTL;NET vga_vsync LOC="P99" | DRIVE = 2;NET vga_hysnc LOC="P97" | DRIVE = 2;