haxtormoogle

have you actually tested this? I still get RPC getwork errors while trying to send work to the fpga. in the async_receiver there is the parameter ClkFrequency that is set to 20000000 , or 20mhz. the papilio one's clock is 32mhz right? same issue with the module async_transmitter

I got the Verilog_Xilinx_Port to synthesise and was abble to generate a bitstream file I could upload to the papilio. Issues start when I try to connect to the uart and do mining. I might have the tx and rx ports reversed or something, The other possibility is or there may be with the timing. Original code was written for a 20 mhz crystal not 32. Any suggestions as to how i can go about debugging?

I have been doing a bit of reading. Turns out that there has been code written to mine on the Spartan 3E 500K. https://github.com/teknohog/Xilinx-Serial-Miner I was wondering if anyone has attempted to get this to work on a Papilio one? I don't really care about mining speeds, I more want to learn how to program fpgas to do very complex things