I got the Verilog_Xilinx_Port to synthesise and was abble to generate a bitstream file I could upload to the papilio. Issues start when I try to connect to the uart and do mining. I might have the tx and rx ports reversed or something, The other possibility is or there may be with the timing. Original code was written for a 20 mhz crystal not 32. Any suggestions as to how i can go about debugging?