Bytter

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  1. Thanks Jack, worked like a charm :-)
  2. Thanks Jack for the answer; providing me some hints is already a big help and ought (hopefully) to be enough :-) It doesn't seem as straightforward as just connecting the two pins. ISE gives me the following error: Error: branch 'RXD' and branch 'WING_AL0' cannot be joined, because both branches have an I/O marker.Hmmm. Should create a dummy component with TX_IN, RX_IN, TX_OUT, RX_OUT and just assign the INs to the OUTs?
  3. From the documentation: I would like to use the internal FT2232 in the Papilio Pro as a simple USB-to-UART (for programming an Arduino, for example), but it seems the RX and TX pins are not connected to the headers. What is the fastest way to use the internal FT2232 to achieve such a thing? P.S. Maybe upload a program for the FPGA that merely connects the RX and TX (P101 and P105) to two other arbitrary pins?
  4. Power Papilio Pro from a 3v3 source

    Jack, Just tested and it worked great, thanks :-)
  5. Power Papilio Pro from a 3v3 source

    Since the oscillator, flash and memory are all working through 3v3 (if I'm not missing something in the diagrams), wouldn't a direct power injection on one of the 3v3 wing pins do the trick? ---- Ok, VCCINT requires 1.2v :-\
  6. I'm wondering if it is possible to power the Papilio Pro directly using a 3v3 source (in my case, I want to use a 3.7v LiPol battery + linear regulator), instead of the usual 5V.
  7. ZPUino on ppro

    Hey Alvie, Thx for all the help so far :-) The FPGA_LED_PIN macro worked like a charm, and the led keeps blinking in the typical 'hello world - blink led' sketch, so the ZPU seems to be running. However, the communications over the Serial Port remains problematic. The ASCII Table sketch stops at the same point, and it is related to the Serial.print(thisByte); Commenting this line out seems to fix. If I try different values for thisByte, then, for some completely obscure reason for me, anything below 80 trashes the serial and eventually freezes. o.O
  8. UART Demo on Papilio Pro

    Actually... The above code works pretty well... The thing is that the configured baud rate is 3000000 (3Mbit/s!!!). I've pushed the papilio pro's migration to here: https://github.com/hugoferreira/uart-example-papilio-pro I searched Gadget Factory's github for a repo to fork this code, but I couldn't found it. If there exists such a repo, please drop a note and I'll do a pull request.
  9. UART Demo on Papilio Pro

    And the corresponding UCF: ## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.CONFIG PROHIBIT=P144;CONFIG PROHIBIT=P69;CONFIG PROHIBIT=P60;NET "extclk" LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLKNET "rx" LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RXNET "tx" LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX
  10. UART Demo on Papilio Pro

    Ok, the following was as far as I could go. I used the Xilinx's KCPSM6 for the uart_tx and rx, and configured the UCF for the Papilio Pro but I still don't receive any kind of echo in the COM port. Here's the code: library IEEE;use IEEE.STD_LOGIC_1164.ALL;library UNISIM;use UNISIM.VComponents.all;entity UARTExample is Port ( rx : in std_logic; tx : out std_logic;LED1 : out std_logic; extclk : in std_logic);end UARTExample;architecture Behavioral of UARTExample iscomponent uart_tx6 isport ( data_in : in std_logic_vector(7 downto 0); buffer_write : in std_logic; buffer_reset : in std_logic; en_16_x_baud : in std_logic;buffer_data_present : out std_logic;serial_out : out std_logic;buffer_full : out std_logic;buffer_half_full : out std_logic; clk : in std_logic);end component; component uart_rx6 is port ( serial_in : in std_logic; buffer_read : in std_logic; buffer_reset : in std_logic; en_16_x_baud : in std_logic; clk : in std_logic; data_out : out std_logic_vector(7 downto 0); buffer_data_present : out std_logic; buffer_half_full : out std_logic; buffer_full : out std_logic);end component; COMPONENT dcm32to96PORT(CLKIN_IN : IN std_logic; CLKFX_OUT : OUT std_logic;CLKIN_IBUFG_OUT : OUT std_logic;CLK0_OUT : OUT std_logic);END COMPONENT; signal dout : STD_LOGIC_VECTOR (7 downto 0);signal data_present, en_16_x_baud, clk : STD_LOGIC;signal baud_count : integer range 0 to 5 :=0;beginbaud_timer: process(clk)beginif clk'event and clk='1' thenif baud_count=1 thenbaud_count <= 0;en_16_x_baud <= '1';elsebaud_count <= baud_count + 1;en_16_x_baud <= '0';end if;end if;end process baud_timer;impl_uart_tx: uart_tx6port map ( data_in => dout, buffer_write => data_present, buffer_reset => '0', en_16_x_baud => en_16_x_baud, clk => clk, serial_out => tx,buffer_data_present => LED1,buffer_half_full => open, buffer_full => open);impl_uart_rx6 : uart_rx6port map ( serial_in => rx, buffer_read => '1', buffer_reset => '0', en_16_x_baud => en_16_x_baud, clk => clk, data_out => dout, buffer_data_present => data_present,buffer_half_full => open,buffer_full => open);Inst_dcm32to96: dcm32to96 PORT MAP(CLKIN_IN => extclk,CLKFX_OUT => clk,CLKIN_IBUFG_OUT => open,CLK0_OUT => open); end Behavioral;
  11. ZPUino on ppro

    Oh yeah, now I see it... :-) It seems able to upload sketches now, great! Two things: (1) Does anyone know what is the "arduino-level" port of the internal led? (P112?) And (2) when uploading the "ASCII Table" sketch, serial monitor (or putty) only receives the following: "ASCII Table ~ Character Map !, dec:" ... and it stops. Resetting the board leads to the same result. Thoughts?
  12. ZPUino on ppro

    Here's the error: Binary sketch size: 892 bytes (of a 12160 byte maximum)Board: Unknown board @ 96000000 Hz (0xa4041700)Verification failed at 0x00060000!00 00 10 00 31 0a fa de a4 04 17 00 0b 0b 0b a0 94 04 00 00 0b 0b 0b 0b 88 08 0b 0b 0b a0 90 2d 0b 0b 0b 0b 88 0c 04 00 00 00 00 00 02 d0 05 0d 00 40 09 00 00 00 00 00 80 00 00 00 00 14 04 00 01 02 88 00 00 20 00 25 13 00 00 10 00 00 00 00 20 00 00 08 01 00 00 01 00 10 20 90 0c 00 00 01 08 04 00 00 40 00 00 00 00 80 10 20 40 00 00 00 88 00 00 00 00 00 00 00 00 80 00 00 00 00 24 00 00 00 00 00 00 08 00 00 04 40 00 80 01 01 02 0a 00 00 10 09 04 01 00 00 01 00 02 20 00 00 00 00 00 10 03 00 00 02 00 00 00 00 00 01 00 01 04 a0 00 00 00 00 04 00 00 80 40 51 02 98 00 01 00 00 00 00 00 02 00 00 40 08 00 00 a8 04 08 00 00 04 00 00 80 00 00 04 04 00 00 01 80 18 00 20 80 00 00 80 04 00 50 00 00 00 00 00 80 00 00 01 00 02 21 a0 40 00 00 10 01 00 00 00 00 00 00 50 08 00 00 df 58 e2 31 0a fa de a4 04 17 00 0b 0b 0b a1 df 04 00 00 0b 0b 0b 0b 88 08 0b 0b 0b a0 df 2d 0b 0b 0b 0b 88 0c 04 00 00 00 00 00 02 f8 05 0d 80 52 8d 51 a0 e0 2d 02 88 05 0d 04 02 f4 05 0d 81 52 8d 51 a0 f4 2d af d7 c2 80 70 52 53 a1 f0 2d 80 52 8d 51 a0 f4 2d 72 51 a1 f0 2d 02 8c 05 0d 04 04 04 70 80 c8 80 80 90 52 a0 fc 04 70 80 c8 80 80 a0 52 a0 fc 04 70 81 90 0a 52 a0 fc 04 72 0a 83 2b 0a fc 06 72 05 70 08 81 75 9f 06 2b 76 88 38 09 06 71 0c 50 51 04 07 71 0c 50 51 04 71 70 33 86 38 72 31 88 0c 04 81 05 a1 9d 04 a8 08 04 02 f8 05 0d a6 f8 52 71 a6 fc 2e 93 38 71 70 84 05 53 08 51 70 2d 71 a6 fc 2e 09 81 06 ef 38 02 88 05 0d 04 04 a0 a8 2d a0 b8 2d a0 b8 2d a1 d6 04 02 f8 05 0d a1 ae 2d 80 52 80 51 a1 d3 2d a1 ed 04 02 f4 05 0d 80 cc 80 80 8c 70 08 76 Programming completed WITH ERRORS in 0.83 seconds.According to this topic http://forum.gadgetfactory.net/index.php?/topic/1588-how-to-program-the-arduino-sketch-for-zpuino-to-the-spi-flash/page-2, I should replace the programmer .exe file in the tools folder... But my tools folder doesn't have any subfolder named zpu, nor any binary inside.
  13. ZPUino on ppro

    Actually, now that I was able to synthesize and bitstream it to the FPGA, the ZPUino IDE gives me a verification error whenever trying to upload anything. I don't have my Papilio Pro here, but once I arrive home, I'll post the message.
  14. ZPUino on ppro

    Thanks for the tip :-) Unfortunately, I have the following error: ERROR:NgdBuild:604 - logical block 'slot14/sid/fblk.filters' with type 'sid_filters' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'sid_filters' is not supported in target 'spartan6'.Ideas? UPDATE: Nevermind... Missing files.
  15. UART Demo on Papilio Pro

    Hi, I've tried following your tutorial on getting the UART demo running on the Papilio, but it seems things are a little different with the 'Pro' version. Particularly, the Spartan 6 version of the Microblaze doesn't seem to have the VHDL top-level directory, and when importing the UART files it fails to synthesize. Any thoughts?