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About kb1gtt

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  1. From the below, I see a symbol search path can be added to the sch2hdl command. I think the lack of this switch could be the problem, or at least one possible solution. Here's what I get when I run the below to get some help from this command. When I request a functional model in ISE, I get the below in the console. I notice the sch2hdl command does not have the above noted -sympath so to me it makes sense that it can't find the symbols. I checked this on the windows machine, however it doesn't echo the command, so I don't know if this switch is used in windows. I did get an echo with a different command, which also did not include the switch. So I suspect the the symbol path is being done with an environment variable or something similar. I wonder how I verify the symbol path, or how I add it to that command. Also to fix the red box issue, I simply drag the end of the wire over one box, and it re-attached correctly. So that's appears to be a minor problem.
  2. I finally got ISE installed on windows 7, and got to compile this project. It seems to compile just fine on Windows, so I would agree with jack the problem seems to be a Linux issue. I would guess it's a / vs \ issue somewhere. I do see some oddities on both windows and Linux, in that I get these red box things on the right side of the symbol, however the red box things don't seem to be that much of an issue, the tracks route, and such. I wonder if these can be an indication of some underlying issue. I also wonder how to fix the Linux issue, perhaps I should create a new project and try to attach the files by hand. I kind of doubt that would work, as I suspect the issue is found in one of the sources.
  3. kb1gtt

    ZPUino on ppro

    This sounds good Process "Generate Post-Place & Route Static Timing" completed successfully So at least it compiles now, and doesn't toss errors. I posted my complete project forked and found here. https://github.com/jharvey/ZPUino-HDL/tree/lsu I can't seem to find a bit file to upload into the FPGA though.
  4. kb1gtt

    ZPUino on ppro

    I'm using ISE and trying to make a project based on the project file. I don't know how to use the makefile, I assume it will require specific compiler tools installed, which I probably do not have installed.
  5. kb1gtt

    3d printed papilio pro cases

    Sweet, it looks good.
  6. kb1gtt

    ZPUino on ppro

    I tried https://github.com/alvieboy/ZPUino-HDL.git switched to the lsu branch, then I used the two files (sid_filters.vhd and sid_coeffs.vhd) which I found in Jack's repo. I got the same results as posted above. I also found those couple missing .vhd files here http://netsid-papilio.googlecode.com/svn/trunk/ and still no dice.
  7. kb1gtt

    ZPUino on ppro

    I have bumped into some problems getting the ZPUino to compile correctly. I also posted an ISE project file in hopes that once these issues are overcome, it can make it easier for others to start using this. See files posted here. http://code.google.com/p/daecu/source/browse/#svn%2Fmisc%2FFPGA%2FZPUino-HDL_project Currently I get an error message as noted below. Annotating constraints to design from ucf file"/home/jharvey/Desktop/papilio_SOC-master/gadgetfactory/ZPUino-HDL/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/papilio_pro.ucf" ...Resolving constraint associations...Checking Constraint Associations... Done... Checking expanded design ...ERROR:NgdBuild:604 - logical block 'bootmux' with type 'wbbootloadermux' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'wbbootloadermux' is not supported in target 'spartan6'.ERROR:NgdBuild:604 - logical block 'zpuino/core' with type 'zpu_core_extreme_icache' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'zpu_core_extreme_icache' is not supported in target 'spartan6'. Partition Implementation Status------------------------------- No Partitions were found in this design. ------------------------------- NGDBUILD Design Results Summary: Number of errors: 2 Number of warnings: 0 Total REAL time to NGDBUILD completion: 14 secTotal CPU time to NGDBUILD completion: 11 sec One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "papilio_pro_top.bld"... Process "Translate" failed I have been googling this and fumbling around, but haven't figured it out yet. Any suggestions on what to look for or how to correct this such that it compiles?
  8. Hello OmniTechnoMancer, I certainly will look to learn more about VHDL, it's one reason why I look at this SOC effort. I'm certainly a NOOB to FPGA and learning this as I go. The schematic editor is a great way to help me get a feel for how the hipbone and leg bone connect before getting into the lower levels of VHDL. I think the concepts of doing it without a schematic is a bit different from Jack's goals. This thread title specifically notes with schematic editor. So I posted about some of the bumps in the rug I hit, and posted info such that these bugs can be ironed out. I think the issue is a mild schematic cache issue, I probably just have to click a button somewhere to flush the buffer.
  9. The symbol schematic shows a graphic, however it appears to not be the correct graphic as it has all that red, and there is an unused port hanging off the end where you appear to have added some stuff to the symbol. I used the "browse" button to get the path setup in the lib manager. I have also looked into the noted sch2HdlBatchFile batch file, and everything I see appears to have the correct path. I also don't see any / vs \ issues, however I feel I don't see the actual commands so who knows if it's using / or \ at that point. There are no spaces, case sensitivity looks good, I even had it regenerate some of the files like the batch file just to double check. I think that with it showing the old graphic, what we are seeing is an issue with a cached copy of the old / original symbol. It seems like when I re-ran the symbol lib manager pointing it to the newer .lib, it simply didn't stick. I tried to re-run it and specify remove, of the zpuino core, however the core still showed as an option for me to select under the symbol tab. I don't see how this can happen unless there is a cached copy some where. Perhaps I need to flush the buffer some how. I can install this on a windows machine perhaps Wednesday and see if I'll have the same problem in windows.
  10. kb1gtt

    3d printed papilio pro cases

    It looks interesting. I have blown a board before by accidentally pulling it half off the edge of my bench, which has a metal edge. I got that board working again, however I never really fully trusted it after that. Any chance you might consider also making some cases for the mega wings? I've got a retrocade. Will you be able to do the bridge across the USB connector? I would think that would need some kind of filler material or something. Perhaps a two piece setup would work better, such that you make the bridge by bolting on a lid. I think it's currently about 2X as tall as it needs to be, the mini USB connector and XTAL are both about the same height, and only 3.9mm (.152in) tall. There is a jumper that's taller, however it's only one jumper. Also it looks like you made it thinner under the A, B, C connectors, Perhaps that can be made thin enough that if someone wants to grow down instead of up, then can cut out the bottom with a razor or something. It might also be good to add holes such that wings can be bolted on.
  11. Hello Jack, I've been absorbing the great FPGA book, and now I'm starting to look at the SOC thing again, hopefully with less ignorant eyes I just downloaded the above zip file, and extracted to a folder titled Papilio_System_On_Chip_jack I moved the symbols location to this new folder, however it still appears I don't have the correct ZPUino symbols. When I open Papilio_SOC_Base.xise then click the green arrow, I get this in the console. Also when I open the schematic, I get the below. Perhaps you have your symbols pointing to a different directly than what I have it pointed to. Mine are point to /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip_jack/xilinx_libs/Papilio_SOC.lib I extracted the zip file to /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip_jack/ I get very similar with LogicStart.xise which is the other ise project that is included in the zip file. I found a project under ./soft_processors/ZPUino-HDL/zpu/hdl/zpuino/boards/papilio_one/ that came close compiling.
  12. kb1gtt

    Papilio Pro Beginner Tips

    I buggered it but it appears I have found the correct bit file. Or at least this one seems to react the same as what was in it. Blinking the LED and communications over putty. My goal was to verify the file, however I buggered it, and overwrote it with an incorrect bit file. When I first opened the programmer, I choose to scan and verify, however when I choose the bit file, it auto-selected write to flash, which I didn't notice. Oops. I programmed it with the below and it appears to be doing something again. /blah/Test-Plans-master\Papilio_Pro_Verification\bin\QuickStart-Zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.04.bit I see what EJK means about out-dated web pages. I grabbed version 1.3 at first, however the below is part of 1.4. Now it's time to play with some of my own stuff. Lets see how well I can bugger it
  13. kb1gtt

    Papilio Pro Beginner Tips

    I got my Pro last night yipee! The above post section "1. Windows FTDI Drivers:" worked for me. It appears my Pro came with a firmware installed, as I see the LED1 blinking at about a 1 second rate, and the RX LED is also blinking. Following the above, I got putty to connect a port as 9600/8/n/1 and I see a bunch of stuff coming out of it. I had to change the CDM uninstaller product ID to 0x6010 it was originally 6001. After this change, when I hit "add", it showed a device was attached. which I then removed. To find the 6010 I didn't see the ID under device manager, in my case WIN7 64x is virtual under Ubuntu, so I used a terminal and lsusb to find the below. Bus 004 Device 029: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC After removal, it grabbed different drivers. I also think that if I had installed the loader before I connected the USB it would have grabbed the correct drivers from the start. However I got eager and plugged it in then though, now what. So if you install the program first, you probably won't have to do the uninstaller thing. In either case, you will probably have to do the VCP thing. I then checked the VCP (?Virtual Com Port?) option and re-plugged the USB. After it came up again, it registered as a mouse with a com port. However putty couldn't connect. So I again re-plugged it and then putty could connect. Setting putty for the com port, I got a bunch of this stuff 123, dec: 123, hex: 7B, oct: 173, bin: 1111011124, dec: 124, hex: 7C, oct: 174, bin: 1111100125, dec: 125, hex: 7D, oct: 175, bin: 1111101 I see I have loader 2.1, so I'm golden there. What I wonder now, before I try to upload something, can I download the firmware that's in this? Such that if / when I break it, I can re-install this firmware. Also Hamsters book is great, it also worked quite well for me. About the only significant question I've had so far is a question about the speed setting when creating a new project. I had -3 and -2 as options. I assumed -3 was slightly slower and perhaps more reliable, so I guessed the default -3 was what I wanted. I have also taken some snap shots of config screens and such as I followed the book. I plan to send those screen captures his way once I verify these variations work. For now, it's off to the salt mine, will get to play a bit more when in about 10 hours. Yipee!
  14. I feel sheep-ish right now. I figured out the problem with github and finding Papilio_Default.vhd. It appears I was looking for the .vhd files under the zip project not the github project. Sorry for buggering that and thanks for the help/support. When setting the symbol location, where should the schematic draw path point? I set it to the same folder as the xlinx.libs, as that has lots of space to work with, and it defaulted to that folder as I had just set the symbol location. However it appears I still have a symbol problem when using the github copy of the project. I'm assuming it wants some place where there is lots of space. I currently get this error message, when I try to view functional HDL model. Command Line: sch2hdl -intstyle ise -family spartan3e -flat -suppress -vhdl Papilio_SOC_Base.vhf -w /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip-master/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.schERROR: Failed to load symbols for /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip-master/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch no netlist will be generatedERROR: Could not find symbol "zpuino_empty_device"ERROR: Could not find symbol "ZPUino"ERROR: Could not find symbol "Papilio_Default" When I set the symbols, and I'm at the last dialog of setting the symbols, I get a note that the libs have to be saved to the same folder as the schematic symbols. Perhaps that's the problem, and I don't have the schematic draw path correct. I'm still fumbling through this.
  15. I set the symbols per the SOC sneak peek video which allowed the schematic to show correctly. Before adding the symbols the schematic failed. Also those files don't appear under the stuff I've downloaded, so i don't think the issue is with a missing link, I think the problem is that I don't have those files. I have downloaded the git copy, and zip copy, and placed them in different folders. I can change between the two projects by simply opening the other project. Perhaps these files are included in a different file that others happened to use. I looked in the LogicStart files, but only found the .ucf. Could they be under a different project like the arcade?