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  1. rgeries

    Driving multiple DCMs

    Or is this more of a routing issue rather than IBUFG's drive capability?
  2. rgeries

    Driving multiple DCMs

    Ah ok. I didn't try a second internal clock buffer. I will try this out as soon as I get a chance. Thank you for your help. Just out of curiousity, do you know if the IBUFG just can't drive multiple DCMs? And if so would it also help to buffer this signal (clkin1) to all of the DCMs and not exclude the first DCM?
  3. rgeries

    Driving multiple DCMs

    My bad that was a mistype in this post. I am using IBUFG.
  4. Hello, I recently ran into a problem driving multiple DCM's from a single external clock source. Ive looked around for solutions and become familiar with Xilinx's documentation for the Spartan's DCM layout. The problem is that you cannot drive more than one DCM from the same external signal because when mapping it will try to duplicate the input clock buffer [1]. The solution is that you must buffer the external signal using IBUF and specifiy the DCMs to be driven by this internal signal. I've implemented a buffer to do this [2] and drive each DCM with this buffered signal. However, I still run into mapping errors when compiling the project. I am not on a computer with my source code or mapping errors at the moment, however I wanted to see if anyone had any insight about this. References: [1] http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Two-parallel-DCMs-on-Spartan3e/td-p/182856 [2] http://www.cs.indiana.edu/hmg/le/project-home/xilinx/ise_8.1/doc/usenglish/de/libs/lib/ibuf4816.pdf
  5. rgeries

    help! vhdl... melting... brain...

    This should probably work. First problem (Have to use the IEEE libraries): scrMem := scrMem + to_integer(unsigned(vCounter(3 downto 0))); Second (This isn't copy and paste you have to define these in the right places): signal Nbit : std_logic_vector(2 downto 0); Nbit <= hCounter(2 downto 0); if (cdata(Nbit) = '?') then ? else ? end if;
  6. rgeries

    32Mhz Oscillator for Papilio pro

    Even with a 27 MHz oscillator you would still want to use a DCM to clean up the clock signal.
  7. I realize this is a two year old thread. However, here is a straight VHDL code example written by Steven J. Merrifield to read and write raw data onto a SDSC card (via SPI interface). This can be altered to write to a higher capacity SD. http://forums.xilinx.com/t5/Spartan-Family-FPGAs/VHDL-SD-card-interface-using-PmodSD/td-p/207037 Jack did you ever get around to writing your own VHDL code for this? If so would you still be willing to share it?