Raypfaff

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  1. Raypfaff

    Xilinx ISE error - new to FPGA

    You are correct. Swapping the rx/tx seems to make it work. It took me a little while to check it, but the code seems to run. I say "seems" bacause the chip gets a little hot and I'm assuming the default clock speed isn't correct. It's not a fire danger, but I'm playing with FPGA bitcoin mining using an Cyclone IV chip I picked up for $15, so I wasn't willing to risk burning out the Papilio. I ran it for about 15 minutes, but it would be a miracle to get a nonce by that time. However the miner.py code is communicating with the board. If anyone wants to continue playing with it, you'll need python installed plus the pyserial module and a jsonrpc module (just check out the readme contained in the project.)
  2. Raypfaff

    Xilinx ISE error - new to FPGA

    Yeah, that appeared to fix it, but I'm not entirely sure why. Here's my ucf. I switched Tx and Rx from what the original mega wing logic board had, The code compiles, but I haven't tried uploading it yet. This is the ucf that I'm using, I assume that the segments aren't quite right on it. ## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.#CONFIG PROHIBIT=P99;#CONFIG PROHIBIT=P43;#CONFIG PROHIBIT=P42;#CONFIG PROHIBIT=P39;#CONFIG PROHIBIT=P49;#CONFIG PROHIBIT=P48;CONFIG PART=XC3S500E-VQ100-4; NET "osc_clk" LOC = "P89"; # serial port receive & transmitNET "RxD" LOC = "P88";NET "TxD" LOC = "P90"; # 7 segment display, in the order that fpga4fun usesNET "segment<7>" LOC = "P23";NET "segment<6>" LOC = "P62";NET "segment<5>" LOC = "P35";NET "segment<4>" LOC = "P33";NET "segment<3>" LOC = "P53";NET "segment<2>" LOC = "P40";NET "segment<1>" LOC = "P65";NET "segment<0>" LOC = "P57"; NET "anode<0>" LOC = "P67";NET "anode<1>" LOC = "P60";NET "anode<2>" LOC = "P26";NET "anode<3>" LOC = "P18"; #NET "led<7>" LOC = "R4";#NET "led<6>" LOC = "F4";#NET "led<5>" LOC = "P15";#NET "led<4>" LOC = "E17";#NET "led<3>" LOC = "K14";#NET "led<2>" LOC = "K15";#NET "led<1>" LOC = "J15";#NET "led<0>" LOC = "J14";
  3. Raypfaff

    Xilinx ISE error - new to FPGA

    When I compile the serial miner, I get this. Never seen this error before, so I'm not sure if it's something I messed up in the ucf file or this has something to do with the board itself. Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible. The component type is determined by the types of logic and the properties and configuration of the logic it contains. In this case an IO component of type IOB was chosen because the IO contains symbols and/or properties consistent with output or bi-directional usage and contains no other symbols or properties that require a more specific IO component type. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. There are no symbols "below", just this error.
  4. Raypfaff

    Xilinx ISE error - new to FPGA

    Thanks very much for the help! Sorry, I should have said I was using the Xilinx code in the projects folder. I guess that I was using the IDE incorrectly. I'm at work and it's not in front of me, but I tried using a "find all" command that I assumed would look in all the source code for the term "DCM_BASE". I guess the command didn't work in the way I had interpreted it, as it came back with nothing found.
  5. Raypfaff

    Xilinx ISE error - new to FPGA

    Hamster, I'll give that a try. I assumed that DCM_BASE wasn't correct, but the 3E does support DCM, so I assumed the name wasn't correct (since it says it's not supported in the 3E) and I was trying to figure out where it's coming from. Alvieboy, for some reason I can't paste the link, but if you google "open source bitcoin miner", it's about 4 entries down. The github link. It's supposed to run on the Cyclone and Spartan, specifically the Spartan 6.
  6. Raypfaff

    Xilinx ISE error - new to FPGA

    Not that either. I'm running 14.3 You can select Spartan 3E and the board as XC3S500E, so I assumed it supported the Papilio. Thanks for telling me though, so I don't upgrade it.
  7. Raypfaff

    Xilinx ISE error - new to FPGA

    I would have to see if I can verify that, but it doesn't look like it. There doesn't seem to be an IP for DCM, unless it's embedded in something else I'm using. If I recall DCM's just a primitive.
  8. Raypfaff

    Xilinx ISE error - new to FPGA

    I've gone through some of the basic tutorials for writing in VHDL and I decided to play around with the open souce bitcoin miner. Before the thread gets hijacked, yes I know I will make no money. It's just a fun little project. When I try to create a program using the ISE Webpack tool, I get the following warnings/errors. NgdBuild:486 - Attribute "FACTORY_JF" is not allowed on symbol "dcm" of type "DCM_BASE". This attribute will be ignored. WARNING:NgdBuild:486 - Attribute "PHASE_SHIFT" is not allowed on symbol "dcm" of type "DCM_BASE". This attribute will be ignored. WARNING:NgdBuild:486 - Attribute "STARTUP_WAIT" is not allowed on symbol "dcm" of type "DCM_BASE". This attribute will be ignored. ERROR:NgdBuild:604 - logical block 'dcm' with type 'DCM_BASE' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'DCM_BASE' is not supported in target 'spartan3e'. There are, I think, several more warnings having to do with DCM_BASE. I "think" that the problem is that DCM_BASE really needs to be DCM. However, I can't find the definition of DCM_BASE in either the VHDL or in the .ucf file. Does anyone have any idea what the problem here might actually be?