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About RonCK

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  1. Jack, Is the default baud rate of 9600 changeable for the uart.vhd that is included in the Papilio_AVR project for the Papilio One? I have an external Bluetooth device that insists on 115200 for the startup communications, though it can be slowed down after that. Thanks, RonCK
  2. RonCK

    Custom Cores with Xilinx ISE 14.4?

    Victory! Well, mostly. I updated the Arduino software and then had to make a change to the script file to update the custom.bit directory as they moved. At least now when I hit upload in Arduino both my HDL and my C code are working. Best regards, Ron
  3. RonCK

    Custom Cores with Xilinx ISE 14.4?

    Xark, Thank you, that helped a great deal. Now the output file from ISE works. I am apparently fighting two problems though as the Arduino generated uploads still don't work. If I synthesize again with the updated ROM image the ISE generated file works. I compared the papilio_avr8.bit != the out.bit file in the Arduino build directory. Are you using Jack's Arduino IDE0018g? Best regards, Ron
  4. RonCK

    Custom Cores with Xilinx ISE 14.4?

    Xark, I suppose that is possible. I was unable to use the core builder until I added this environment variable: XIL_CG_LOAD_ALL_FAMILIES = TRUE. Then the IP cores were usable. I have continued my debug and now I seem to be able to run HDL code in the chip as long as I have no C loaded into the Arduino and I can run C, but doing so seems to shut off my functionality to the port A pins. I'm guessing at this point that there is something buried in the Arduino C libraries that is causing the problem but I have no idea what to look for. Best regards, Ron
  5. Jack, I'm using your v1.6 Aurduino Soft Core with the template for a custom user core enabled. I have port A fully assigned and driven freely by the HDL code in the custom core. I can download the synthesized .bit file directly from ISE and I see the port A pins responding. I've used the copy-to-custom.cmd script to copy the bit file over to the Arduino directory. I can then compile essentially any code and see in the verbose output that the ROM file has been updated in the Xilinx directory. I can simulate this and see the port A pins do what I expect them to. But, if I download the output .bit from the Arduino compiler as soon as setup() completes, the core loses control of the port A pins. Any idea why this would be the case? I started with the cImplPORTA generate constant defined as FALSE and the cImplpapilio_core_template as TRUE and have tried numerous combinations to where I now have completely commented out everything in the top level hdl file related to port A and the user core and have greatly simplified my port A code and put it directly in the top module (and changed the porta pin definitions to be out only) and have seen no change in the behavior with HDL + Arduino code. Any help would be appreciated. (current top level hdl code attached) best regards, Ron Papilio_AVR8.vhd
  6. I'm working on the tutorial on simulating custom cores and have notice that the Arduino tool only calls the makefile routine when I select upload. Can I force it to call the make file on a verify? thanks, RonCK
  7. Jack, The new version seems to be working for me. Thank you much! Best regards, Ron
  8. Thanks Jack, That fixed the issue with the loader that I had. I'm now working through your tutorials and am having problems with the AVR8 Custom Core. When I first tried it I got an error that looked similar to those referenced here: and here: except that I'm using Xilinx ISE 14.4. I tried copying data2mem.exe from my Xilinx directory to Arduino/Hardware/Tools/Butterfly_Platform along with the Microsoft.VC90.CRT folder that was there, but I'm now getting this error: Merging Verilog Mem file with Xilinx bitstream: make: *** [pcustom] Error -1073741515 My Google searches are returning nothing as to what that could be. Is anyone else using ISE 14.4 yet and has solved this? Best regards, Ron
  9. OK, I fixed the first one myself. The trick was editing properties on the instance of "USB Serial Converter B", "Advanced", Selecting "Load VCP" then unplugging and replugging in the Papilio One. I'm still hoping that someone can help with the second, as it bugs me that I don't get to see the confirmation screen on loading a bit stream. Best regards, Ron Cummings-Kralik
  10. Hi Jack et al, I've got my Papilio One 500k hooked up to my Windows 7-32bit laptop and I can download bit streams with the Papilio Loader. When I download the Quick Start/Hello World bit stream I can see that I have 2 instances of the the FTDI USB Serial Converter loaded but I have no COM ports available. I know that the PC has pushed the bit stream as I see the alternating states on the even pins but I can't see how to proceed with the ASCII table part without having a COM handle assigned. I see on this forum that others have had this issue and resolved it but not the necessary techniques to duplicate their success. Any suggestions would be useful. On a slightly related note, how do I configure the Papilio Loader to not automatically exit until I can read the result. I had to lengthen the timeout in the file initial dialog as it was too short even read the options before it started loading, but the other visible timeout in the script seems tied to a failed load only. Thanks in advance. Best regards, Ron Cummings-Kralik