SteveD

Hi Tom, you'll find that SRAM is a lot more beginner friendly than SDRAM. Bang for buck SDRAM is cheaper per bit than SRAM but it's a lot harder to get it working with the FPGA. Am not sure how the boards stack up price wise but my personal preference would be the Duo. Cheers, SteveD

Hi Cactus, according the the Spartan 6 Family Overview (http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf) the chip is compatible with several low voltage families from 3.3V down to 1.2V. From the Papilio Pro schematic it looks like all 4 IO banks are supplied from the 3.3V rail. So i'd say ok to connect with 3.3V logic, do not connect to 5V logic. More information on the IO capabilities here: http://www.xilinx.com/support/documentation/user_guides/ug381.pdf Cheers, Steve

Hi Eric, Pong Chu gives excellent tutorials on SDRAM interfacing and VGA control in his books on FPGA programming. Based around the Diligent S3 board but should port easily to the Papilio world. Cheers, Steve

Hi, the short answer is yes, the retrocade wing could be used to build a digital alarm clock. The display would be very small. Have you considered using one of these? http://www.gadgetfactory.net/logicstart-megawing/ It has a much larger LED display. Easier to see night and day. Functionally you will need: 1) Oscillator pulsing at 1Hz. Research the Spartan DCM module. 2) Some counters, e.g. hours, minutes 3) Display control logic e.g. binary to 7 segment converter, display multiplexer. Most digital electronics texts will show you how. Wakerleys "Digital Design" (4th ed) is an excellent source.

Hi Jack, you're welcome. Feel free to redistribute. Probably not clear from the code but it uses dual ported RAM to store all 8 samples (adcReg). Data is available externally through use of addr inputs and q outputs.

I use the following code to process ADC input from a Retrocade mega wing. That board has 2x8bit ADC chips communicating over SPI. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // // Engineer: Stephen Davies // // Create Date: 21:05:48 10 Jan 2013 // Design Name: // Module Name: ADC // Project Name: MiniMoog sim // Target Devices: Spartan 6 // Tool versions: ISE 14.4 // Description: State machine logic for polling a TI ADC088S102 ADC chip. // Logic operates in a loop, polling the current port value in a // single 'frame'. Each input port (of 8) is sampled in its own // frame, delimited by CS, so that synchronisation is maintained. // // A future implementation could make the frames larger, querying all // 8 ports in a single frame. This would improve throughput. Maximum // throughput would sample each individual port @125k samples/s. Per port // framing reduces this a little but not enough to worry about given // that the main function for the analog pins is to attach pots & switches. // // Dependencies: // // Revision: 0.01 // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module ADC #( parameter ADC_WIDTH=8 // ADC sample size in bits ) ( input clk, // 16 MHz clk (max for ADC088S102) input reset, // active high output sck, // SPI clock (16MHz max for ADC088S102) output reg cs_n, // ADC chip select, active low input din, // data stream from ADC chip, sampled on rising edge of SCK output reg dout, // data stream to ADC, ADC chip samples on rising edge of SCK input [2:0] addr, // register read address output [ADC_WIDTH-1:0] q // register output value ); // State machine states localparam RESYNC = 1'b0; // ADC chip select (CS) taken high localparam SAMPLE = 1'b1; // ADC chip select (CS) taken low, analog data being sampled // Variables reg [6:0] count; // 7 bit counter, low order 4 bits count 16 SCK pulses per frame. // high order 3 bits indicate current port wire [2:0] currentPort; // port we are receiving dataIn for reg [4:0] dataOut; // Output shift register, contains next port address and two 0 bits. Not all 16 bits are required as unused bits default to 0. reg [15:0] dataIn; // Input shift register, contains current anaolg sample plus padding wire [2:0] nextPort; // next analog port to be read, sent as part of current dataOut frame wire endFrameTick; // indicates end of frame has been reached, drives FSM through RESYNC state (* RAM_STYLE="DISTRIBUTED" *) reg [ADC_WIDTH-1:0] adcReg [7:0]; (* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="RESYNC" *) reg state = RESYNC; // FSM state (at initial state) assign endFrameTick = &count[3:0]; // at end EOF when count == 4'b1111 assign currentPort = count[6:4]; // values 0-7 assign nextPort = currentPort + 3'd1; assign q = adcReg[addr]; // // FSM // always@(posedge clk, posedge reset) if (reset) begin // system reset state <= RESYNC; count <= 7'b0; cs_n <= 1'b1; end else (* PARALLEL_CASE, FULL_CASE *) case (state) RESYNC : begin // immediately moves to SAMPLE state after resetting key values state <= SAMPLE; count <= { count[6:4], 4'b0 }; // preserves nextPort value cs_n <= 1'b0; end SAMPLE : begin if (endFrameTick) begin // when 15 SCK cycles have occurred, RESYNC for next analog port state <= RESYNC; count <= count + 7'd1; cs_n <= 1'b1; end else begin // keep on clocking... state <= state; count <= count + 7'd1; cs_n <= 1'b0; end end default: begin // Fault Recovery state <= RESYNC; count <= 7'b0; cs_n <= 1'b1; end endcase // // DOUT shift register, selects next port to sample // 5 bits long because first 3 bits are zero, next 3 are port and next 10 are zero. // always @(negedge clk, posedge reset) if (reset) begin dataOut <= 5'b0; dout <= 1'b0; end else if (cs_n) begin // load register at start of frame dataOut <= { nextPort[0], nextPort[1], nextPort[2], 2'b0 }; dout <= 1'b0; end else if (!cs_n) begin // shift next bit dataOut <= { 1'b0, dataOut[4:1] }; dout <= dataOut[0]; end // // DIN shift register // always @(posedge clk) if (!cs_n) dataIn <= { dataIn[14:0], din }; else adcReg[currentPort] <= dataIn[11:4]; // // Spartan 6 requires special handling for sending clk16 on SCK pin. (not a 'special' clock output pin apparently) // ODDR2 ODDR2_inst (.Q(sck), .C0(clk), .C1(!clk), .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0)); endmodule

Lee, have you given any thought to turning your circuit idea into a wing? I for one would like to experiment with audio processing eg. mixing, filtering, effects. Having a board with several possible line, guitar, balanced mic inputs and several line outputs would be neat. Steve PS. Don't know what your background is but would be happy to work with you if PCB design isn't your thing.

Hi Lee, in ISE 14 you now toggle between implementation and simulation views in the top left panel. You can add test benches/fixtures (vhdl vs. verilog) to test on a per module basis. Perform a behavioral syntax check before running the simulation model. Running the model opens the iSim application window and with a little tweaking you will see nice graphs of your inputs and responses. Cheers, Steve

Lee, nothing says you have to use the 32MHz clock as your reference. Viable alternatives could be to: 1) replace existing oscillator with one of a different frequency 2) add a second oscillator on one of the many broken out GCLK pins Steve

Hi Lee, Alex seems to have a better handle on this than me so I'll keep it general. First, sounds like you need to learn about clock management on Spartan 6. Each Spartan 6 has a number of digital clock managers (DCM's). These are special function blocks on the FPGA that allow clock signals to be manipulated in various ways. They can divide and multiply the 32MHz signal in interesting ways. See http://www.xilinx.com/support/documentation/user_guides/ug382.pdf Given that 48kHz is an even integer fraction of 32MHz (4000/6) it shouldn't be too hard to pick an intermediate frequency, say 5.666MHz (1/6) and work from there. The CLKFX pin is probably what you're after. The Xilinx ISE deisgn software has a wizard to help configure the DCM in either VHDL or Verilog. I'll be interested in what you come up with as I intend to implement a simple mixer as part of my Minimoog project. Cheers, Steve PS. If it were up to me i'd start out by implementing with a 16 bit signal simply because the S6 hardware multipliers are 18x18 bits. Using a 24 bit word makes muliplication that little bit trickier.

Thanks Alvie, I'll look into it. Steve

Hi all, just comitted a fix to the ADC logic and it is now working correctly. Module ADC.v contains a state machine that reads each of the 8 analog pins in turn and stores the 8 bit value in a dual ported RAM. While based on the Papilio Pro/Retrocade wing combo it wouldn't take too much fiddling to adapt it to other platforms.

Hi Jack, think I have found a problem in the Retrocade schematic. It's ADC related. The pin names for the SPI controls on ADC1 and ADC2 are reversed. For example, SPI ADC1 is connected to 4 controls, all identified as 'ADC2_*'. Ditto for ADC2. Schematic elements SPI ADC1 and SPI ADC2 are consistent with the PCB silkscreen, it is the signals that are mixed up. The problem is also carried through to the UCF file. Pins for ADC1 are in fact controlling ADC2. Regards, Steve

Hi Jack, sounds good, always happy to share. In case anyone is interested: 1) clock logic cleaned up 2) work started on oscillator bank 3) MIDI keyboard interface not yet started

Hi all, I'm using the Papilio Pro/Retrocade hardware in a slightly different way. I am attempting to replicate a Minimoog synth using DSP techniques. The source code is available at https://github.com/sjdavies/minimoog. So far the system does the following: 1) performs digital->analog conversion using a 12 bit delta-sigma DAC (as per Xilinx doco). 2) generates a sawtooth/square/pulse waveform for a given MIDI note number. 3) samples all 16 analog port pins, latching each value in distributed RAM. Not much but it's a start. Next tasks: 1) clean up the clock logic 2) get a MIDI keyboard attached and working. Enjoy, Steve