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Everything posted by mkarlsson

  1. mkarlsson

    Windows 10 and ISE

    Are you installing the plain ISE14.7 or the special 14.7 Windows 10? The Windows 10 version is actually a virtual machine running Linux. The instructions above is for the plain 14.7 version.
  2. mkarlsson

    Windows 10 and ISE
  3. See comment #3 that states that the MS Natural Keyboard 4000 does NOT work with the USB-to-PS/2 adapter.
  4. Most likely the problem is with the USB-to-PS/2 dongle. The simple passive USB-to-PS/2 dongle only works if the keyboard can switch to use PS/2 protocol. See Magnus
  5. mkarlsson


    ISE on Win10 is broken and wont work unless you takes a few steps. See this post:
  6. mkarlsson

    SRAM timing

    Looks like you have the polarity of /OE wrong - it should be high when writing and low when reading. Magnus
  7. mkarlsson

    Unable to program FPGA on Duo

    No need to use the Oracle VM to run ISE on Win10, just follow these steps: 1) Install ISE14.7 for Windows (Embedded Edition) on your Win10 computer 2) Go to C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 (assuming 64-bit Win10) and rename libPortability.dll to libPortability_orig.dll 3) Make a copy of libPortabilityNOSH.dll and rename it libPortability.dll 4) Go to C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64 and rename libPortability.dll to libPortability_orig.dll 5) Copy libPortability.dll from C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 to C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64 6) Run ISE and install your license file etc. You should now have a working version of ISE on your Win10 computer. Magnus
  8. mkarlsson

    Place:1108 in a XC6SLX16-CSG324

    Here is the problem - you take the signal from the button connected to pin C4 and use that as a clock for the ledst0 flip-flop. This is not how you use an FPGA. Pin C4 is not a clock input pin, which cause the error 1108 you see, and logic signals like btnl should not be used as a clock. FPGAs are intended to be used for synchronous logic designs where a large number of flip-flops are clocked with a common clock. In order to make this possible the clock is distributed to all the flip-flops in this clock domain using special clock buffers and clock networks. The source of the clock is typically coming from an input pin on the FPGA and only a select few pins can be used as clock input. The input clock can be used as is or can be feed to a clock management tile that has resources like PLLs and DCMs that allow you to create a clock with different clock frequency. The Nexys3 board has a 100 MHz clock input signal connected to pin V10 that can be used as system clock. This is what the Nexys3 manual states: Try this code instead: .ucf file: BTW, your switch might "bounce", so you might have to de-bounce the signal from the switch. See What is debouncing? Magnus
  9. mkarlsson

    Changing the clock frequency

    No, the CMT can't do that. If some part of the logic needs to advance at a slow rate, the common way to do that is to use a clock-enable signal, i.e. clock the logic with the system clock (say 32 MHz) and then generate a clock-enable signal using a counter (in your case a 23-bit counter) that resets at the period you want (in your case at 6399999). The clock-enable signal is true when the counter is at the max value (in your case 6399999) and is used to qualify the clocking of the slow circuit. Hope this helps
  10. mkarlsson


    Cool! Yeah, winter is Sweden is not for the faint. As for Arty, I do have one too, and to make it a bit more useful I designed a pmod add-on board with the stuff missing compared to Pipistrello.
  11. mkarlsson


    Most issues now fixed, like intro music and intermission music. Complete project can be downloaded here: Doom first level video (youtube)
  12. mkarlsson


    Got the OPL2 integrated into the Doom project. Still a few rough edges but getting close... Doom on FPGA board (youtube)
  13. mkarlsson


    Well, I do have a github account but have been bad at updating it. The opl3 code for pipistrello can be downloaded here: The latest doom bitfile for pipistrello is here: The latest doom c source code is here: Without support for Spartan6 in Vivado and no more updates for ISE, the old Spartan6 boards are unfortunately getting obsolete, and with the subsidized pricing of the Digilent Arty boards etc. there is very little incentive for me to develop Artix7-based replacement boards Kalmar is a nice place with a castle and all. We have an apartment in Örebro that we use as a home base in Sweden.
  14. mkarlsson

    SoundBlaster FM HDL

    I think I nuked too many files in the ipcore_dir folder for it to compile so I just downloaded the whole project again, this time with all the files. If you have problems building it just re-download the zip file. Magnus
  15. mkarlsson

    SoundBlaster FM HDL

    Here is a video of it running on a Pepino LX9 board: If you have a Pepino LX9 board and want to try it, here is how: Download the zip file and unzip it somewhere Place the files in the dro directory on a micro-sd card and put it in the sd-card socket on Pepino Open up a terminal (like Putty) at 115200 baud connected to the Pepino board Load or flash the bitfile opl2player.bit in the opl2player director At the promt on the terminal, enter the name of the dro-file you want to play (it will loop forever). Stop it by entering S. BTW, the code should work on a Papilio Pro by modifying the .ucf file to match the pins for the sd-card and audio wings and re-synthesize. Magnus
  16. mkarlsson

    SoundBlaster FM HDL

    Bringing this old thread back to life... In my quest to get a fully working version of Doom (including music) running on Pipistrello I found Greg's OPL3 project and decided to port it to Verilog as he mentioned above, and got it running on Pipistrello, as well as an OPL2 version running on Pepino LX9 (100% of slices occupied!). It uses a Microblaze_mcs processor with 32K ram to play .dro files. Here is a link to a zip file with the Pepino_lx9 project (including Verilog sources and a simple dro-file player): Video of it running on Pipistrello: Cheers, Magnus
  17. mkarlsson


    Hi Alex, long time no hear.. I made the opposite trip some 30 years ago (Sweden to US) but still have my roots there and go back several times a year (actually going there this coming Wednesday). I finally got around to work on one of my old projects that I left unfinished - Doom running on Pipistrello. The project was based on a port of Chocolate Doom to the NIOS soft processor by two guys from Finland and I got it to sort of work but had not realized how much they had sacrificed to get it to work on NIOS. The sound system was completely hacked up (8 channel stereo sound effects cut down to a single mono channel with no volume control) and the game crashed at the end of the first level due to non-implemented stuff. So I put back the original code from Chocolate Doom so the game worked and got the full sound system working by porting over the sound mixing from the Linux version of doom. I also added mouse support so the game is now really playable. The only thing really missing now is to play the music tracks. They were implemented in a format similar to MIDI and played on DOS via an OPL2 or OPL3 chip found on some sound cards. I looked around I found that Greg Taylor had done a clone of OPL3 using systemVerilog running on a ZYBO board so I decided to try a port of that code to plain Verilog (since ISE do not support systemVerilog). After some stuggle (systemVerilog has some powerful features that are hard to replicate in Verilog) I got it to work - both the full OPL3 and cut-down version that only support the OPL2 features (Doom only use the OPL2 subset). The OPL2 version fits in an LX9 together with a Microblaze_mcs system. Here is a link to a video showing it running: Next thing is to incorporate it into the doom version. Cheers, Magnus
  18. mkarlsson

    Flash Erase

    See page 77 in this document: The flash chip is erased in units (aka sectors) of 64kB so programming a 65kB bitfile will erase a 128kB area. Magnus
  19. 1) download this tar file 2) untar the file somewhere on you computer (7-zip can do this for you) 3) go to the location of the untar'ed files and run xsetup.exe 4) after installation you need to fix a few things in order to have it run on win10. See The PlanAhead part is optional (not needed for DesignLab)
  20. mkarlsson

    How does data get from the PC to the Spartan-6 Flash

    Xilinx call it indirect programming. See The second serial port is available as a regular serial port (virtual COM port) to the user for any purpose. It's commonly used with a soft CPU to implement an embedded system. Magnus
  21. mkarlsson

    How does data get from the PC to the Spartan-6 Flash

    Almost got it right First a a flash programming bitfile is sent to the FPGA via JTAG. This bitfile uses a special library component (BSCAN_SPARTAN6) that allows the logic fabric to access the JTAG port. Flash SPI programming commands are then sent to the FPGA via JTAG, which will forward them to the flash chip. Magnus
  22. A new version of the Open Bench Logic Sniffer code is now available for Pipistrello. This version has the capture buffer increased to 64 MB by using the onboard LPDRAM instead of using internal BRAM. The capture rate is still the same, i.e. it still support 200 MHz 8 and 16-bit capture as well as 100 MHz 32-bit capture. The serial communication speed is set to 921600 baud. The original SUMP protocol unfortunately has a capture size limitation (in both hardware and software) to a maximum of 256k samples (512k samples in mux mode). This version of the verilog code has an alternative set of capture size registers that will allow up to 256M samples. However, the SUMP client on the PC must be modified to take advantage of the new registers so I have modified JaWi's OLS client to allow longer captures. BTW, the bit file will also work with the current release of the SUMP client but with the capture size limitation mentioned above. Here is a link to a zip file that has the bit file, the full Xilinx ISE project and the modified version of JaWi's OLS client: Enjoy! BTW, if anyone is interested in using the built-in DRAM memory controller in Spartan-6 parts this code might be a good starting point. It's setup to use one 64-bit read/wire port but this can be changed by using different parameters when instantiating the memory controller block.
  23. mkarlsson

    Open Bench Logic Sniffer with 64MB capture buffer

    Sorry but I stopped following the sigrok/pulseview stuff years ago since the development was in my view not the way to go unless you are prepared to do all the compiling yourself. Windows is supported in a very limited way with the nightly build of whatever development code they have that day. However, you can build the windows installer of the last release code on a Linux system yourself if you follow the instructions. The biggest problem is that on windows you need to replace the FTDI driver for the FT2232 chip with a driver based on the Linux libftdi driver. I have not managed to get that working since early 2014. This is really a question to the sigrok team though.
  24. mkarlsson

    Back to Basics

    At work we have switched most of our Spartan-6 products to Artix-7 and for the most part the switch-over was painless, the only area that needed a bit work was places in the code where we directly instantiated low level design elements (like serdes blocks, BSCAN_SPARTAN6 etc.) that had to be re-coded using 7 series elements, and the new way of setting contstrains. However, one area that Xilinx keep messing up is LVDS outputs, which we use lots of. On the Spartan-6 part that we used, only 2 of the 4 banks could have LVDS outputs. On Artix-7 all banks can have LVDS outputs but the bank must have VCCIO set to 2.5V! This means that Digilent boards like Arty and CMOD A7 and Avnet boards like miniZed etc. can't do LVDS output at all since all banks are powered by 3.3V! This is pretty lame since LVDS is the future for high speed I/O, just look at UHS-II sd-card standard where 2 LVDS pairs are added for high speed applications. As for my FPGA "hobby" busyness, I have no desire to develop an Artix-7 or Zynq based board and compete with heavily subsidized products from Digilent and Avnet. And there won't be any more Spartan-6 based boards made by me either (Pipistrello LX45 and Pepino LX25 are sold out and discontinued and once the Pepino LX9 boards are sold there won't be any more boards made). End of the road... I totally agree. I have a long history of designing custom chips, starting in the 1980's with schematic-based design entry for ASICs. When we switched to text-based design entry (i.e. HDL) in the 1990's the productivity gain was incredible. We could do much more complex designs and still understand what it did, and we could use all the tools developed for software to maintain the code (like CVS for code repository, using the text editor that we liked most for design entry, and simple things like text compare). Going back to schematic-based design entry is in my mind a huge step back. Magnus
  25. mkarlsson

    SPI to initialize TFT

    For a more detailed description of the first line see Magnus