mkarlsson

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mkarlsson last won the day on March 30 2019

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About mkarlsson

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  1. mkarlsson

    Windows 10 and ISE

    Are you installing the plain ISE14.7 or the special 14.7 Windows 10? The Windows 10 version is actually a virtual machine running Linux. The instructions above is for the plain 14.7 version.
  2. mkarlsson

    Windows 10 and ISE

    https://www.micro-nova.com/xilinx-ise-win10 https://www.xilinx.com/support/answers/62380.html
  3. See comment #3 that states that the MS Natural Keyboard 4000 does NOT work with the USB-to-PS/2 adapter.
  4. Most likely the problem is with the USB-to-PS/2 dongle. The simple passive USB-to-PS/2 dongle only works if the keyboard can switch to use PS/2 protocol. See https://superuser.com/questions/1150204/can-any-usb-mouse-or-keyboard-be-connected-to-the-ps-2-connector-of-a-motherboar Magnus
  5. mkarlsson

    ISE

    ISE on Win10 is broken and wont work unless you takes a few steps. See this post:
  6. mkarlsson

    SRAM timing

    Looks like you have the polarity of /OE wrong - it should be high when writing and low when reading. Magnus
  7. mkarlsson

    Unable to program FPGA on Duo

    No need to use the Oracle VM to run ISE on Win10, just follow these steps: 1) Install ISE14.7 for Windows (Embedded Edition) on your Win10 computer 2) Go to C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 (assuming 64-bit Win10) and rename libPortability.dll to libPortability_orig.dll 3) Make a copy of libPortabilityNOSH.dll and rename it libPortability.dll 4) Go to C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64 and rename libPortability.dll to libPortability_orig.dll 5) Copy libPortability.dll from C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 to C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64 6) Run ISE and install your license file etc. You should now have a working version of ISE on your Win10 computer. Magnus
  8. mkarlsson

    Place:1108 in a XC6SLX16-CSG324

    Here is the problem - you take the signal from the button connected to pin C4 and use that as a clock for the ledst0 flip-flop. This is not how you use an FPGA. Pin C4 is not a clock input pin, which cause the error 1108 you see, and logic signals like btnl should not be used as a clock. FPGAs are intended to be used for synchronous logic designs where a large number of flip-flops are clocked with a common clock. In order to make this possible the clock is distributed to all the flip-flops in this clock domain using special clock buffers and clock networks. The source of the clock is typically coming from an input pin on the FPGA and only a select few pins can be used as clock input. The input clock can be used as is or can be feed to a clock management tile that has resources like PLLs and DCMs that allow you to create a clock with different clock frequency. The Nexys3 board has a 100 MHz clock input signal connected to pin V10 that can be used as system clock. This is what the Nexys3 manual states: Try this code instead: .ucf file: BTW, your switch might "bounce", so you might have to de-bounce the signal from the switch. See What is debouncing? Magnus
  9. mkarlsson

    Changing the clock frequency

    No, the CMT can't do that. If some part of the logic needs to advance at a slow rate, the common way to do that is to use a clock-enable signal, i.e. clock the logic with the system clock (say 32 MHz) and then generate a clock-enable signal using a counter (in your case a 23-bit counter) that resets at the period you want (in your case at 6399999). The clock-enable signal is true when the counter is at the max value (in your case 6399999) and is used to qualify the clocking of the slow circuit. Hope this helps
  10. mkarlsson

    Boo

    Cool! Yeah, winter is Sweden is not for the faint. As for Arty, I do have one too, and to make it a bit more useful I designed a pmod add-on board with the stuff missing compared to Pipistrello.
  11. mkarlsson

    Boo

    Most issues now fixed, like intro music and intermission music. Complete project can be downloaded here: https://github.com/Saanlima/Pipistrello Doom first level video (youtube)
  12. mkarlsson

    Boo

    Got the OPL2 integrated into the Doom project. Still a few rough edges but getting close... Doom on FPGA board (youtube)
  13. mkarlsson

    Boo

    Well, I do have a github account but have been bad at updating it. The opl3 code for pipistrello can be downloaded here: http://www.saanlima.com/download/pipistrello-v2.0/opl3_pipistrello_lx45.zip The latest doom bitfile for pipistrello is here: http://www.saanlima.com/download/pipistrello-v2.0/doom.bit The latest doom c source code is here: http://www.saanlima.com/download/pipistrello-v2.0/mb_doom_sound3.zip Without support for Spartan6 in Vivado and no more updates for ISE, the old Spartan6 boards are unfortunately getting obsolete, and with the subsidized pricing of the Digilent Arty boards etc. there is very little incentive for me to develop Artix7-based replacement boards Kalmar is a nice place with a castle and all. We have an apartment in Örebro that we use as a home base in Sweden.
  14. mkarlsson

    SoundBlaster FM HDL

    I think I nuked too many files in the ipcore_dir folder for it to compile so I just downloaded the whole project again, this time with all the files. If you have problems building it just re-download the zip file. Magnus
  15. mkarlsson

    SoundBlaster FM HDL

    Here is a video of it running on a Pepino LX9 board: http://www.saanlima.com/videos/IMG_4882.mov If you have a Pepino LX9 board and want to try it, here is how: Download the zip file opl2_pepino_lx9.zip and unzip it somewhere Place the files in the dro directory on a micro-sd card and put it in the sd-card socket on Pepino Open up a terminal (like Putty) at 115200 baud connected to the Pepino board Load or flash the bitfile opl2player.bit in the opl2player director At the promt on the terminal, enter the name of the dro-file you want to play (it will loop forever). Stop it by entering S. BTW, the code should work on a Papilio Pro by modifying the .ucf file to match the pins for the sd-card and audio wings and re-synthesize. Magnus