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mkarlsson last won the day on December 7 2016

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  1. mkarlsson

    Flash Erase

    See page 77 in this document: The flash chip is erased in units (aka sectors) of 64kB so programming a 65kB bitfile will erase a 128kB area. Magnus
  2. 1) download this tar file 2) untar the file somewhere on you computer (7-zip can do this for you) 3) go to the location of the untar'ed files and run xsetup.exe 4) after installation you need to fix a few things in order to have it run on win10. See The PlanAhead part is optional (not needed for DesignLab)
  3. mkarlsson

    How does data get from the PC to the Spartan-6 Flash

    Xilinx call it indirect programming. See The second serial port is available as a regular serial port (virtual COM port) to the user for any purpose. It's commonly used with a soft CPU to implement an embedded system. Magnus
  4. mkarlsson

    How does data get from the PC to the Spartan-6 Flash

    Almost got it right First a a flash programming bitfile is sent to the FPGA via JTAG. This bitfile uses a special library component (BSCAN_SPARTAN6) that allows the logic fabric to access the JTAG port. Flash SPI programming commands are then sent to the FPGA via JTAG, which will forward them to the flash chip. Magnus
  5. mkarlsson

    Open Bench Logic Sniffer with 64MB capture buffer

    Sorry but I stopped following the sigrok/pulseview stuff years ago since the development was in my view not the way to go unless you are prepared to do all the compiling yourself. Windows is supported in a very limited way with the nightly build of whatever development code they have that day. However, you can build the windows installer of the last release code on a Linux system yourself if you follow the instructions. The biggest problem is that on windows you need to replace the FTDI driver for the FT2232 chip with a driver based on the Linux libftdi driver. I have not managed to get that working since early 2014. This is really a question to the sigrok team though.
  6. mkarlsson

    Back to Basics

    At work we have switched most of our Spartan-6 products to Artix-7 and for the most part the switch-over was painless, the only area that needed a bit work was places in the code where we directly instantiated low level design elements (like serdes blocks, BSCAN_SPARTAN6 etc.) that had to be re-coded using 7 series elements, and the new way of setting contstrains. However, one area that Xilinx keep messing up is LVDS outputs, which we use lots of. On the Spartan-6 part that we used, only 2 of the 4 banks could have LVDS outputs. On Artix-7 all banks can have LVDS outputs but the bank must have VCCIO set to 2.5V! This means that Digilent boards like Arty and CMOD A7 and Avnet boards like miniZed etc. can't do LVDS output at all since all banks are powered by 3.3V! This is pretty lame since LVDS is the future for high speed I/O, just look at UHS-II sd-card standard where 2 LVDS pairs are added for high speed applications. As for my FPGA "hobby" busyness, I have no desire to develop an Artix-7 or Zynq based board and compete with heavily subsidized products from Digilent and Avnet. And there won't be any more Spartan-6 based boards made by me either (Pipistrello LX45 and Pepino LX25 are sold out and discontinued and once the Pepino LX9 boards are sold there won't be any more boards made). End of the road... I totally agree. I have a long history of designing custom chips, starting in the 1980's with schematic-based design entry for ASICs. When we switched to text-based design entry (i.e. HDL) in the 1990's the productivity gain was incredible. We could do much more complex designs and still understand what it did, and we could use all the tools developed for software to maintain the code (like CVS for code repository, using the text editor that we liked most for design entry, and simple things like text compare). Going back to schematic-based design entry is in my mind a huge step back. Magnus
  7. mkarlsson

    SPI to initialize TFT

    For a more detailed description of the first line see Magnus
  8. mkarlsson

    SPI to initialize TFT

    idle is set to 1 if all bits in counter are 1 (unary reduction operator AND) if internalSck is high then cs is set to 0
  9. mkarlsson


    Hi Tim, Cool. I will include the Linux version. Yeah, the sigrok p-ols driver is fifo mode only. In serial mode the (i.e. with a serial mode bitstream loaded and the FT2232H is serial mode) the board is basically a Open Bench Logic Sniffer with higher baud rate (921600 instead of 115200) and more memory (64MB instead of 24kB) and it should be trivial to modify the sigrok ols driver to support pipistrello in serial mode. Note that the SUMP protocol limits the samples to 256k so if you want to sample more you need to use the extended range registers that I added (see the p-ols driver). As for the sampling of TMDS data, you should be able to use the HDMI connector for that but you would need to add the 50 ohm terminator resistor packs on the bottom side of the board (the layout is prepared for this). Initially the plan was to support both HDMI-out and HDMI-in and an earlier XL9 board I made worked great in both modes but I was sloppy when I did the Pipistrello layout and did not place the CLK pair on GCLK pins . However, if you just want to asynchronously sample the TMDS data at 4x the bit rate then this should work fine since you don't use the CLK pair as an input clock. You would need to change the Pipistrello OLS code to use SERDES for sampling the data etc. but you should be fine from memory bandwidth standpoint (4 bits at ~1Gb/s is 500 MB/s and the memory controller on Pipistrello can easily do that when using the maximum burst length). If you want to work on this then I can hopefully give you a hand. Cheers, Magnus
  10. mkarlsson


    Should be back now. Please note that this code is for Pipistrello and might have to be modified for other boards. Magnus
  11. No, that's not "equivalent" - you did not declare wb_data_i in the verilog version like you do in the vhdl version so it defaults to a single wire. Try this: input [100:0] wishbone_in; wire [31:0] wb_dat_i; assign wb_dat_i = wishbone_in [59:28]; Magnus
  12. mkarlsson

    Unknown Papilio Board

    On DUO there is a third possible reason for this error - the FT2232H chip on this board has two jtag controllers (port A and port B ) and if papilioprog is trying to open the wrong one you will get this error. If that's the case then one option is to specifically open the correct port using the "-d device name" option. Without the -d option papilioprog will open the first one it finds.
  13. mkarlsson

    Unknown Papilio Board

    This cryptic error message means that it can't find a jtag device connected to the FTDI chip (the error message have been changed in later versions of papilioprog). There are two possible cause for this error - you either have several FTDI devices connected to the computer and papilioprog is talking to the wrong one, or the papilio board has a problem with the jtag wiring from the FTDI chip to the FPGA. Magnus
  14. No, the ft232R does not have an MPSSE unit, which is what the Papilio loader is using for JTAG. Magnus
  15. mkarlsson

    Loading the SPI Flash on the Papilio Pro

    The only difference between my version of the bscan files and the papilioprog bscan files is that I also drive flash_wp and flash_hold. The flash chip on Pipistrello can do quad-spi mode where flash_wp and flash_hold are used as data lines. The pullups on the board for those two lines are too weak to overcome the default spartan6 pulldown on unused pins so I define them as inputs. See attached file. Magnus bscan_spi_spartan6.vhd