OmniTechnoMancer

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Everything posted by OmniTechnoMancer

  1. Hi, I recently purchased a Papilio Pro and RetroCade Synth wing from SeedStudio. When I attempt to program a bit file to the SPI flash the loader complains that the flash manufacturer is unknown, what do I need to do to program the SPI Flash on the Papilio Pro?
  2. OmniTechnoMancer

    32 x 32 LED panel with animations and video

    If you read the description of that it would not be very useful as each voltage terminal is fused at 1.25A so not useful for supplying 10A@5V unless you want to short/change the fuse.
  3. OmniTechnoMancer

    XThunderCore is taking shape

    Perhaps we should start a new thread if this discussion continues. I have not tried it with larger programs, but the instruction sizes scale directly with the number of transport buses and the short immediate width of those buses as the slot for a bus has to be wide enough for the short immediate that can be used on it. If you use an immediate unit and long immediates with a few busses you can shorten the short immediate sizes but still keep the ability to use 32bit immediate values. Aside from the instruction width I guess the issue is mostly how many instructions you can fit in the blockrams available and whether your processor is able to be used efficiently by your program, resulting in fewer overall instructions. Also you have to be careful since the transport bus connection logic is the most resource consuming part usually, you don't want every bus connected to ever FU in the processor.
  4. OmniTechnoMancer

    XThunderCore is taking shape

    The software here http://tce.cs.tut.fi/ can be used to design them and has a C compiler.
  5. OmniTechnoMancer

    XThunderCore is taking shape

    Perhaps use a TTA processor instead?
  6. OmniTechnoMancer

    MAX5556 Audio DAC Wing

    It's not really doing ethernet if you dont use just a PHY on the wing
  7. OmniTechnoMancer

    FPGA in asynchronous mode

    Don't ever use a signal as if it were a clock, and, at least for VHDL don't have any processes that have if's and assign signals in only one branch (this will cause the synthesis to generate storage elements).
  8. OmniTechnoMancer

    FPGA in asynchronous mode

    It isn't an asynchronous mode. You simply either use the flip-flops and clock or you don't, you can use entirely combinational logic if you want.
  9. OmniTechnoMancer

    Can't directly write 0 over serial

    Well its probably the char* and int overloads causing it as 0 could be either, note that you need to use '\0' if you want a character with value zero sent on the serial rather than the digit 0
  10. OmniTechnoMancer

    Papilio Sigma-Delta ADC

    The issue is more that in order to get the conversion noise far enough away from your signal you need to oversample by a significant margin, this will require several hundred megasamples per second to get input on the order of a few MHz, you could try band pass sampling, but for that to work you will need a band pass filter on the input.
  11. OmniTechnoMancer

    Papilio Sigma-Delta ADC

    You might have some issues getting a high enough sample rate if you are doing MHz frequency sampling...
  12. OmniTechnoMancer

    high level programming of FPGAs

    Do you need USB host or USB device, (I assume host as one doesnt usually have more than one device port) if so then it may be better to use one USB core an an external HUB or HUBs to get 30 ports, there are not enough pins on any of the papilios for 30 USB ports anyway needless to say space for 30 host cores in the FPGA, why do you need so many anyway? On the subject of high level development, I personally think that learning digital design is more useful in the long run as it allows you more understanding of what is going on, the high level tools are fine for if what you really want is a computer that instead of being general purpose just does this specific DSP stuff instead but you can't exactly do general purpose digital development with them. And to add new function for the thing Jack is working on one would write a wishbone core in verliog VHDL or use the schematic editor (A bad choice as it will be extremely slow and far less expressive than HDL).
  13. OmniTechnoMancer

    implementing a truth table in vhdl?

    This is a 1 bit ROM implementation. Its the same pattern you use to make ROM but with a std_logic_vector instead of an array of them and the input bits concatenated rather than an address.
  14. OmniTechnoMancer

    A couple of questions

    What Jack is referring to here can be accomplished by a conjunction of loopMIDI and the dashboard, you set the dashboard to take a MIDI input and use loopMIDI to create a MIDI device that can be set as that input but also used as an output for the desired program.
  15. OmniTechnoMancer

    A couple of questions

    The Retrocade ZPUino code implements two MIDI interfaces, one for the MIDI ports on the board and one on the FTDI UART connected to the FPGA, this is what the windows dashboard uses to control the synth. Adding USB MIDI in any way other than buying a USB midi adapter and plugging it into the ports will not be easy, so take this as a no for now. You could access the exposed sound chips the same way that the dashboard does by speaking MIDI over the UART connection, alternatively you could write a different sketch for the board that provides a more suitable interface and use that.
  16. OmniTechnoMancer

    USB specifics for the Pro

    Yes you can change the baud rate on linux whenever, its a standard serial port operation, I don't know if you can use arbitrary rates though, you can definitely pick any of the usual ones like 115200 though.
  17. OmniTechnoMancer

    so what about dsp slices then

    LVDS output and input is the job of the input/output buffers on the FPGA, LVDS has nothing to do with DSP really, it is just a way of transmitting digital data in a way that is immune to common mode noise. DSP blocks are used for multiplication on FPGAs because not only are they faster than a full implementation as hamster said, as long as you don't need a huge number of them they are much less resource intensive than building a multiplier out of logic slices.
  18. OmniTechnoMancer

    so what about dsp slices then

    DSP slices have nothing to do with LVDS, an electrical signalling standard... These are usually used for multipliers when needed because that is basically their primary function, so FIR filters, IIR filters, State Variable filters, Audio processing, anything where you need multiply or multiply accumulate and fast.
  19. OmniTechnoMancer

    USB specifics for the Pro

    For the baud question the answer is that the FTDI chip actually acts as a USB serial port for the PC and the PC configures the baud rate, so you have to set this to the same thing that you are using on the papilio, there is no magic here and you WILL get wrong results if you set it wrong.
  20. OmniTechnoMancer

    Intro To Spartan FPGA Book Error

    I tested a simple module that had 3 inputs and one output, which just did output <= in1 xor in2 xor in3; And when I forced all the inputs to '1' in the simulator the output was '1'. It doesn't matter if it is a 3-input XOR gate or a cascaded series of XOR gates as XOR is a linear operation. In general XOR outputs '1' if there is an odd number of '1' inputs and '0' otherwise, so if you are seeing other behaviour then something is wrong.
  21. OmniTechnoMancer

    Intro To Spartan FPGA Book Error

    I believe you are mistaken, if both x(1), y(1) and carry(0) are all '1' then the result(1) expression resolves to '1' XOR '1' XOR '1', in VHDL results are calculated left to right so this is actually ('1' XOR '1') XOR '1' which comes out to '0' XOR '1' which is easily seen to be '1', thus the expression for result(1) is correct if we have a '1' in both inputs and the carry in, the carry logic then deals with providing the carry out bit for all cases, which gives the other '1' from your example.
  22. OmniTechnoMancer

    New to this tech.

    The boards come programmed with the ZPUino with the quickstart sketch from the factory, this is why your board works as a ZPUino, additionally it seems the UART on the FTDI chip is fine as the IDE can program the ZPU over that. In order to use the board as an AVR8 or Retrocade, the FPGA configuration has to be changed to implement the required hardware, as you can see you are having JTAG issues so this cannot complete successfully. As far as I know for AVR8 the IDE uses a xilinx tool to change the initialisation contents for the blockrams implementing the code memory of the AVR core, this requires a reconfiguration every time you change the code, whereas the ZPUino has a bootlaoder that can load it's code from the flash chip on the board and which can update that code over the serial port.
  23. OmniTechnoMancer

    New to this tech.

    He installed it into a path with spaces in it, this causes this problem, install it in a location without spaces in the path and it should work.
  24. OmniTechnoMancer

    Audio library

    If you want a 3-Osc synth you will probably find that putting the 3 oscillators in hardware will make like much easier. The FFT algorithm would be best done by some kind of co-processor that has operations to make the FFT fast (like FFT blocks for size 2, 3, 5, 7) but since the FFT algorithm requires different work to be done depending on the length of the input it cannot be made into a simple piece of hardware that just gives you the FFT, such an implementation would require a different implementation for every size. Most of the effects you want to do are actually much much much easier to do in VHDL than in software because you can literally have them be a network of busses that clock a sample between modules every sample period, then the modules can do whatever work they do in parallel. The CPU should be saved for things like control that requires many decisions or for other parts that require large numbers of decisions and things that are difficult to implement in hardware.
  25. OmniTechnoMancer

    Access to non wing pins

    I think what he wants to know how to connect something to the ZPUino's timers so that he can have the direction and pulse outputs from the quadrature decoder drive a counter to accumulate the rotation. So basically, does the ZPUino have timers that can be used to count pulses, or would it be better to implement the counter in VHDL and add a quadrature decoder wishbone core to the ZPU?