Adding an UART to AVR8

[Adding an UART to AVR8]

Hello whitewolf,

I haven't forgotten about this, I tried to put together an example this weekend. But I upgraded to Windows 8 and now I'm having all kinds of troubles with the Xilinx tools. So I have to figure out what is going on before I can put the example together for you.

You are heading in the right direction though, the only other thing is that you need to change the register address that the second UART is connected to. So you have to make a copy of the uart.vhdl file and put the register address in the free memory space that the user code examples use.

Jack.

I dont understand which register address and where i can find the free memory space that the user code examples use. I will wait for your example.

Thank you.

.

[Adding an UART to AVR8]

I watched the video, where should i instantiate it ? top level ?

uart_Inst:component uart port map(
   				 -- AVR Control
				    ireset	 => core_ireset,
				    cp2   	    => core_cp2,
				    adr	    => core_adr,
				    dbus_in    => core_dbusout,
				    dbus_out   => uart_dbusout,
				    iore	   => core_iore,
				    iowe	   => core_iowe,
				    out_en	 => uart_out_en,
				    -- UART
				    rxd	    => rxd,
				    rx_en	  => open,
				    txd	    => txd,
				    tx_en	  => open,
				    -- IRQ
				    txcirq	 => core_irqlines(19),
				    txc_irqack => ind_irq_ack(19),
				    udreirq    => core_irqlines(18),
           		 rxcirq	 => core_irqlines(17)
       			 );


-- UART connection to the external multiplexer                              
io_port_out(2)    <= uart_dbusout;
io_port_out_en(2) <= uart_out_en;

making another copy of this uart "uart2" will work ?

Or should I write another uart in papilio_core_template?

Thank you.

[Adding an UART to AVR8]

Hello, I'm wondering if anyone made another uart in avr8 papilio 250k to be used with external peripherals. I tried to edit the vhd files. But its difficult since I'm new to VHDL. I have some experience with Verilog. since Can you give me a VHDL or Verilog example.

Thank you.