cospan

Members
  • Content count

    1
  • Joined

  • Last visited

Community Reputation

0 Neutral

About cospan

  • Rank
    Newbie

Profile Information

  • Gender
    Male

Recent Profile Visitors

89 profile views
  1. Hello, I'm designing a development board and I would like to include a 16bit wing interface. There are certain pins on FPGAs that is optimized for clock input. Is there a standard pin location on the wing that is specified as a clock input? I went through the Papilio Pro schematic and found the following pins were attached to GCLKs W1 A2 W1 A3 W1 A12 W1 A13 W1 A14 W1 B4 W1 B5 W1 B10W1 B14 W1 B15 W2 A9 W2 A10 W2 A11 W2 A12 W2 A13 W2 A14 W2 A15 W2 A16 Which is a surprising number of GCLKs (awesome!). It looks like the pin that is common to them all is 14. So if I were to map an input clock enable pin on at least 14 would this work for wings? Dave