

joesugar
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Everything posted by joesugar
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Wow, this is exactly the thing I'm looking for for a project of mine. Looking forward to see how it progresses.
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I've been working this area on a Papilio One, mostly on the transmit side. So far I've put together an interface for a high speed D2A and have implemented an amateur radio PSK31 modulator. I'm currently working on an I/Q modulator using the CORDIC algorithm. The plan is to read IQ data from a Teensy via an I2S interface and have it function similar to a USRP but at lower bandwidth and frequencies. I've written up the PSK31 modulator at https://ceworkbench.wordpress.com/2014/06/01/a-pks31-beacon-in-an-fpga/and have a bunch of blocks in my githup repo at https://github.com/joesugar/DesignLabSketchBook. Drop me a note if you'd be interested in trading project ideas.
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Hi guys, Anyone here ever do any work getting digital audio data into a Papilio? I'm working to create a waveform generator for amateur radio use using the Papilio One. The idea is to accept data from another computer in I/Q format and upconvert it in the FPGA to produce a signal in the 3 - 30 MHz range. Think a lower-frequency version of the GNU Radio USRP. I'm at the point where I need an interface to read in the I/Q data and am leaning toward creating a block that will impersonate the I2S interface of an audio codec. I'd be satisfied with a bandwidth of around 50 kHz (for now ) and I like how I2S explicitly identifies the right/left channels. However, I'm open to other ideas and thought I'd see if anyone here has done something similar before committing myself. Thanks for any suggestions, Joseph
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Thanks Jack, I'll take a look at it. Joseph
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newbie: why is taking 2 clock cycles to update the output? AKA are statements inside a process() block really sequential?
joesugar replied to flag26838's topic in FPGA Discussions
The quick answer is no. Signal assignments within a process are all done in parallel and for the case you've given, the assigned values are those that exist at the time of the clock edge. I_dataD takes two cycles to propagate to O_dataA because on the first rising edge of the clock I_dataD is latched into regs and O_dataA takes on the value that was in regs when the clock edge occurred. It isn't until the next clock edge (the second) that the original value of I_dataD is available in regs to be latched into O_dataA. Kind of like a bucket brigade. -
I've started converting some of the Wishbone cores I've written in the past for use as DesignLab libraries. So far I have a simple numerically controlled oscillator and am working on updating an interface for the WM8731 audio codec. As part of this, I put together a short explanation of the work flow I use to convert my Wishbone cores for use in DesignLab and posted it at https://ceworkbench.wordpress.com/2015/10/03/adapting-wishbone-cores-for-use-with-the-papilio-and-designlab/. (Sorry, no video.) I'd appreciate any comments or suggestions for improvements. Thanks, Joseph
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Hello everyone. I've had a Papilio One for a while now but this is the first time I've had a question I'm hoping some of you can help with. I'm working on implementing an amateur radio PSK31 transceiver in a Papilio One using the ZPUino soft core. I have the transmit portion working and have started working on the receive portion. To minimize the external hardware required I'd like to implement a sigmal-delta A2D converter. I've run across lot's of articles that discuss the theory but no actual code (be it Verilog or VHDL). Has anyone here implemented such a beast? Can you point me in the right direction for examples I can use as a basis? Thanks for any help or direction you can provide, Joseph
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I was thinking about converting the signal to a single-bit data stream using a sigma-delta circuit, then use a digital down-converter to move the frequencies of interest down to baseband before filtering. Since it's similar to a sigma-delta ADC I hoping to get similar performance.
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You're correct, I have the first two but WOW, how did I miss the third? My original idea was to use a direct conversion receiver feeding the ADC but downconverting the sigma-delta bit stream directly within the FPGA is something that never occurred to me. Definitely going to pursue this. Thanks for the information.