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About KoviRobi

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  1. Hi! I am coming over from http://www1.idc.ac.il/tecs/ and wondering, is it possible to implement the computer described in TECS (and here for ease, quoted from http://nand2tetris-q...0.html#a3517367): Transistor count: (By cadet1620 over at the nand2tetris forums) CPU---------------------1 528 Memory decoding----253 RAM16K---------------4 538 299 ROM32K---------------2 097 088 Screen buffer---------2 793 339 --------------------------------------- Computer--------------9 430 507 Basically, the way it works, is it has a RAM16K for variable memory, a ROM32K for instruction memory, and the screen is mapped into the upper 8K of the RAM16K, just before the keyboard, which is mapped onto the upped 16 bits of the memory. So my question really is, is it possible to implement this in Papilio One (I guess I will need the 500K version, but I was considering buying that anyway.) Thank you! (If something is not clear, ask, and if it is in the wrong place, then please move it, or if it has been answered, I apologise I did not find it.)