craiglindley

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Posts posted by craiglindley


  1. I'm a long time computer programmer and electrical engineer who is just now trying to understand VHDL and FPGAs. I've got some conceptual hurdles I need to get over before I attempt my first design. Probably everyone who is in this field has had these same questions at some point but I could not find the answers by searching the Internet. I'll illustrate my questions with the following VHDL code snippet:

    entity ENTITY is

    port (

    );

    end entity;

    architecture rtl of ENTITY is

    signal instruction : std_logic_vector( 15 downto 0 );

    signal is_alu : std_logic;

    begin

    process1

    begin

    line 1;

    line 2;

    end process1;

    is_alu <= ( instruction(15 downto 13 ) = B"011" ) ;

    process2

    begin

    if (is_alu ) then ….

    end process2;

    end;

    I understand that within a process block the lines of code are executed sequentially. And I think I understand that any assignments made to signals within a process block aren't actually visible until the process block has finished (goes into a wait). Is this true?

    My other questions are:

    1. Do the two process block run in parallel?

    2. Does any code within an entity definition get executed except within a process block?

    3. For example, is the is_alu signal assignment shown between the two process blocks actually only evaluated when it is referenced in process2 block?

    4. Are there any interactions between the process blocks other than those the code I write cause?

    5. If process blocks run totally independently and in parallel how does one guarantee ordered execution of the resultant hardware? This is where I'm definitely missing something and it is probably because of my programming background.

    6. Is there some rule of thumb about the type and/or scope of the functionaliy contained in a process block?

    I'm sure I'll have many more questions but getting answers to these will help alot.

    Thanks in advance

    Craig Lindley


  2. Hello,

    I'm a rank newbie to FPGAs and the various design languages. I've been studying the J1 forth core and pretty much understand most of the Verilog code. The following construct however has puzzled.

    I understand that dsp is the data stack pointer and that it is 5 bits wide for the 32 words making up the data stack

    reg [4:0] dsp; // Data stack pointer

    Here I understand the data stack offset is extracted from the instruction as a 2 bit value

    wire [1:0] dd = insn[1:0]; // D stack delta

    This expression is what I don't understand

    _dsp = dsp + {dd[1], dd[1], dd[1], dd};

    Can anyone enlighten me about what this is doing?

    Thanks in advance