Peter Aus Wyk

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About Peter Aus Wyk

  • Rank
    Member
  • Birthday 10/19/1962

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  • Gender
    Male
  • Location
    Wyk auf Föhr Germany
  • Interests
    photography, animals, restoring my house, vintage computing, hobby electronics
  1. Peter Aus Wyk

    Cant find LX9(Pro) with ZAP Linux IDE ?

    Hello all, anything new on ZAP IDE Linux? I tried the Linux x86 version from Alvie's site on my 64bit Ubuntu. I exchanged the rxtx lib to the 64bit Version and the IDE starts up but no serial port is found (besides this tcp port thinggy) Any advise how to get the ZAP IDE going on a 64 bit Linux? B.t.w. the windows version within wine shows up some com ports but none is found for upload finally (neither ZPUIno in SPI as Loader nor an AVR) Thanks a lot Peter
  2. Peter Aus Wyk

    DiskVaccuum project

    great project for anyone interested in vintage computing and conserving good old treasures. I like the narrative Thank you very much Peter
  3. Peter Aus Wyk

    Reflow oven

    you've seen the videos? It's as hamster stated above. The reflow temperature is really critical in respect to the performance (or even survival) of components... be sure to stay away from the max. temps in the datasheets. So measuring temperature at the body of the oven may mislead and cause real trouble
  4. Peter Aus Wyk

    happy new year

    All the best in 2014.... awaiting my first mistake writing the date Stay healthy Peter
  5. Peter Aus Wyk

    Reflow oven

    Hi I just incidentally run across Dave's latest EEVLOG vids regarding a simple reflow oven kit from germany (Actually this are two links (one shown as a link one shown as a embedded youtube video ) http://www.youtube.com/watch?v=FNNRoXZom30 probably it's already seen but I thought posting this does not hurt
  6. Hi Jack and thank you very much.... I did as you proposed and found the corresponding *.sym files in my project directory. Just for fun I copied them into the Xilinx Library Directory and deleted the sym-files after that in my project directory... eh voila it works I can live with that because it's only to be done once in the "template". For simplicity it may help others to put the *.sym files into the zip file? Many regards and thanks again, made my day Peter
  7. Hi all, sorry for digging out this old thread, but it desribes exactly my problem. After downloading the latest schematc library 1.4 I tried to synthesize the VGA8 example project. I added the symbol directories as described by Jack in the C64 SID video and it looks all ok... The OS here is Linux 64bit ISE is 14.7 (lin64). Any ideas how to use the lib within Linux? Many regards and silent xmas time Peter ERROR: Failed to load symbols for /home/peter/Programming/fpga/fpga/Papilio-Schematic-Library-1.4.1/Papilio_Schematic_Projects/Wing-VGA8/Papilio_SOC_Base_Papilio_One.sch no netlist will be generatedERROR: Could not find symbol "Wing_GPIO"ERROR: Could not find symbol "Wishbone_Empty_Slot"ERROR: Could not find symbol "Papilio_Default_Wing_Pinout"ERROR: Could not find symbol "Wing_VGA8"ERROR: Could not find symbol "VIDEO_zpuino_wb_vga_hqvga"ERROR: Could not find symbol "VIDEO_zpuino_wb_char_ram_8x8_sp"ERROR: Could not find symbol "ZPUino_Papilio_One_V1_hyperion"ERROR: Could not find symbol "clk_32to50_dcm"
  8. Peter Aus Wyk

    SPI Flash and Linux again :(

    thank you so much, indeed that was the solution. I even didn't noticed that there is a preference menu All the best and merry christmas Peter
  9. Peter Aus Wyk

    SPI Flash and Linux again :(

    Hello all, after I searched through the forums and tried different options to no avail I would like to ask here for an opinion My problem is programming a papilio one 500 SPI Flash within Linux, esp. Kubuntu 13.10 Flash works ok and the papilio-loader-gui shows no errors For me all looks good so far. I disconnected and reconnected the USB cable without success. Within a Win 7 64bit everything works like a charm (that is Flash and SPI are configured successfully) Any ideas? Thank you for reading Best regards Peter Using devlist.txtJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500EUsing devlist.txtJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500EUploading "/opt/GadgetFactory/papilio-loader/programmer/bscan_spi_xc3s500e.bit". Done.Programming time 223.0 msProgramming External Flash Memory with "/home/peter/Programming/fpga/1test/encoder_xilinx_bsp/main.bit".Found SST Flash (Pages=2048, Page Size=264 bytes, 4325376 bits).Programming :..............Finished ProgrammingOkDone.SPI execution time 12232.0 msUSB transactions: Write 727 read 10 retries 20Using devlist.txtJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500EISC_Done = 1ISC_Enabled = 0House Cleaning = 1DONE = 1
  10. Peter Aus Wyk

    FPGA... what for?

    Hi Gerard, everything what is possible with the small AVRs/PICs can be done on the P/Pro. You have theSoftcores AVR and ZPUino at hand. The advantage is the possibility to "add" hardware into your projects with much less effort than soldering IC's. As a ham you could for instance start with the frequency counter from Hamsters Wiki and modify it to substract the IF, let's say 455 kHz. What about a rotor control for an antenna? So I started now with the zpuino and the wishbone interface and think there is a learning curve yes, but not as steep as I expected. uC's a great for having everything built in, but when something is missing things get complicated. If you need, let's say 5 rotary encoder with high rpm, you can easily add them to your softcore and not run into interrupt limits or alike. You mentionend some good books and sources, simply try some examples in the isim simulator,, that helps see some effects of VHDL constructs Regards currently inactive DH1AO Peter
  11. Peter Aus Wyk

    Introducing ZAP IDE - ZPUino and AVR8 together at last!

    After I took a look into the device manager I was amazed : round about 15 Bluetooth Device COM Ports.. Some from Toshiba some from a bluetooth controlled panoramci head. After disabling all of them the menu is much more responsive. Now I have to wait 5 to 10 seconds, before it lasted 10 minutes or more. Greetings Peter
  12. Peter Aus Wyk

    Introducing ZAP IDE - ZPUino and AVR8 together at last!

    Hi all, I'm almost unable to choose "tools" from the menu All other menuitems respond but tools doesn't show up. After a while I kill the IDE with the taskmanager. No difference wether the board is plugged in or not. Any ideas? Edit found that at http://arduino.cc/de/Guide/Troubleshooting#toc14 Why does do the Arduino software and the Tools menu take a long time to open (on Windows)?If the Arduino software takes a long time to start up and appears to freeze when you try to open the Tools menu, there by a conflict with another device on your system. The Arduino software, on startup and when you open the Tools menu, tries to get a list of all the COM ports on your computer. It's possible that a COM port created by one of the devices on your computer slows down this process. Take a look in the Device Manager. Try disabling the devices that provide COM ports (e.g. Bluetooth devices).
  13. Peter Aus Wyk

    Wishbone templates for ZPUino

    Hi again, thank you both for the clarification. I myself build sometimes ago a circuit out of "discrete" CMOS ICs to observe a metastable situation on a scope. Indeed it was a very rare event. I mentioned it in my post simply because even if you use Flip Flops you can ran into funny behaviour of a circuit. Current chip technology inherently has enormous high amplification and therefore only a small window in time changes of clock and inputs may lead to metastability. As I read typical delays are in the range of 10 to 100 ps. The probability of a metastable state is less than 10e-10. Maybe in extreme highspeed applications you have to cascade the Flip Fliops (JK, Master/Save) to ensure proper functioning. I have no clue about the metastability issue when you connect to synchronous systems with different clock domains? Metastability possible? Now, after digging in the datasheet Jack linked to, I see my first post is totally useless regarding the original question but anyways, I've got some interesting answers I like to expand the image in my brain Many regards Peter P.S. sorry for my german accented english
  14. Peter Aus Wyk

    Wishbone templates for ZPUino

    Hi synchronous is as far as I know the use of a clocked flip-flop for output signals in contrast to latches. That in turn means a output signal only can change at predefined points in time, etc rising clock. Asynchronous signals can change intermittently before reaching a steady state. This usually happens due to different delays of input signals to a gate. As an example a xor gate with two inputs A and B. Let's assume the XOR output is 0 and the inputs A and B change from A=0 and B=0 to A=1 and B=1 but the B's one arrives the xor gate a little bit later than A's 1 so for a short moment the xor gate will show a 1 on it's output until B's 1 arrived and propagated through the gate. I think this is a hazard or race condition. This asynchronous design can lead you in deep trouble with regard to state machines. Some time ago we had to reconstruct an old ASIC asynch design from mid 80th into a current FPGA. It was hell on earth Maybe that all is understood already, but I thought it could help some readers. Next upcoming question is metastability Cheers Peter
  15. Peter Aus Wyk

    8 digit frequency counter

    ah sorry missed to include the link https://docs.google.com/file/d/0B84N2SrJaybwZTgxYjM4ZmEtY2EyZi00YjVjLWIzOTctYTlhMjJkM2MxMTBl/edit?pli=1