Neon22

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  1. Updated to cascade DCMs. Not using any PLLs. That's a bit harder. Shows different ways a clock can be generated. E.g. for the above mentioned 12.288 and 24.576 Desired Frequency = 12.288For 12.288 MHz. Exact. Use: CLKFX, CLKFX180. For 12.288 MHz: CLKFX_MUL/CLKFX_DIV = 2 / 25 from 153.600000 MHz. For 153.6 MHz. Exact. Use: CLKFX, CLKFX180. For 153.6 MHz: CLKFX_MUL/CLKFX_DIV = 12 / 25.For 12.288 MHz. Exact. Use: CLKFX, CLKFX180. For 12.288 MHz: CLKFX_MUL/CLKFX_DIV = 4 / 25 from 76.800000 MHz. For 76.8 MHz. Exact. Use: CLKFX, CLKFX180. For 76.8 MHz: CLKFX_MUL/CLKFX_DIV = 6 / 25.For 12.288 MHz. Exact. Use: CLKFX, CLKFX180. For 12.288 MHz: CLKFX_MUL/CLKFX_DIV = 8 / 25 from 38.400000 MHz. For 38.4 MHz. Exact. Use: CLKFX, CLKFX180. For 38.4 MHz: CLKFX_MUL/CLKFX_DIV = 3 / 25.Desired Frequency = 24.576For 24.576 MHz. Exact. Use: CLKFX, CLKFX180. For 24.576 MHz: CLKFX_MUL/CLKFX_DIV = 16 / 25 from 38.400000 MHz. For 38.4 MHz. Exact. Use: CLKFX, CLKFX180. For 38.4 MHz: CLKFX_MUL/CLKFX_DIV = 3 / 25.For 24.576 MHz. Exact. Use: CLKFX, CLKFX180. For 24.576 MHz: CLKFX_MUL/CLKFX_DIV = 2 / 25 from 307.200000 MHz. For 307.2 MHz. Exact. Use: CLKFX, CLKFX180. For 307.2 MHz: CLKFX_MUL/CLKFX_DIV = 24 / 25 -Unlikely. (>250MHz. Needs chip speedgrade-2).For 24.576 MHz. Exact. Use: CLKFX, CLKFX180. For 24.576 MHz: CLKFX_MUL/CLKFX_DIV = 4 / 25 from 153.600000 MHz. For 153.6 MHz. Exact. Use: CLKFX, CLKFX180. For 153.6 MHz: CLKFX_MUL/CLKFX_DIV = 12 / 25.For 24.576 MHz. Exact. Use: CLKFX, CLKFX180. For 24.576 MHz: CLKFX_MUL/CLKFX_DIV = 8 / 25 from 76.800000 MHz. For 76.8 MHz. Exact. Use: CLKFX, CLKFX180. For 76.8 MHz: CLKFX_MUL/CLKFX_DIV = 6 / 25. - don't type in 32MHz - the listing is very long I recall now I stopped working on this because the vendor had a special clock helper in the IDE. Other people are better situated to comment on its effectiveness. https://github.com/Neon22/papilio-clock
  2. I used this ref for DCM info (has max internal freqs etc): http://www.xilinx.com/support/documentation/user_guides/ug382.pdf anyone know same ref for papilio Duo ?
  3. Nice work. I had a go at this before too and Hamster nicely posted it on his site. BUt the two chained plls works better than mine. - http://hamsterworks.co.nz/mediawiki/index.php/Papilio_Plus/Clock I also used a brute force method of calculating all possible ratios then sorting the list. Worked quite well and you get to see all possible implementation choices. I wrote it in python but I did not do the two chained timer approach. I need to make an update. Mine was specifically for the Papillio so my max div ratio is 32 not 40. (I may have read the datasheet wrong, or new device is faster ) Of course it all depends on the chipset you're using. I wonder if its worth trying to factor in these per-device limitations ? I'll work on it some more and post a newer version... [..Update..] Latest version here: https://github.com/Neon22/papilio-clock Sample output: Desired Frequency = 22.5792975 clocks evaluatedFor 22.0689655172 MHz. Error = 0.510234 mult1/mult2 = CLKFX, CLKFX180 / CLKFX_MUL/CLKFX_DIV = 2 / 29.For 22.8571428571 MHz. Error = 0.277943 mult1/mult2 = CLKDV / CLKDV_DIV = 14.For 22.8571428571 MHz. Error = 0.277943 mult1/mult2 = CLKDV / CLKDV_DIV = 7 (+CLKIN_DIV_BY_2).For 22.8571428571 MHz. Error = 0.277943 mult1/mult2 = CLKFX, CLKFX180 / CLKFX_MUL/CLKFX_DIV = 2 / 28.Desired Frequency = 224975 clocks evaluatedFor 222.608695652 MHz. Error = 1.391304 mult1/mult2 = CLKFX, CLKFX180 / CLKFX_MUL/CLKFX_DIV = 16 / 23 . Possible (>200MHz internal speedgrade-2).For 224.0 MHz. Error = 0.000000 mult1/mult2 = CLKFX, CLKFX180 / CLKFX_MUL/CLKFX_DIV = 14 / 20 . Possible (>200MHz internal speedgrade-2).For 224.0 MHz. Error = 0.000000 mult1/mult2 = CLKFX, CLKFX180 / CLKFX_MUL/CLKFX_DIV = 21 / 30 . Possible (>200MHz internal speedgrade-2).For 224.0 MHz. Error = 0.000000 mult1/mult2 = CLKFX, CLKFX180 / CLKFX_MUL/CLKFX_DIV = 7 / 10 . Possible (>200MHz internal speedgrade-2).
  4. Neon22

    high level programming of FPGAs

    For the future then - this section doesn't take too long to go through and covers all the basics about how to use it and integrate with VHDL (well mainly verilog but there is some VHDL). Don't jump ahead http://www.myhdl.org/doc/current/manual/index.html
  5. Neon22

    high level programming of FPGAs

    Oops - realised I asked a related Q a year and a half back... but may be more pertinent now re Papiliio schematic editor... - http://forum.gadgetfactory.net/index.php?/topic/1335-quadrature-encoders-and-lcd/?hl=myhdl#entry8167
  6. Neon22

    high level programming of FPGAs

    Jack - what's your opinon on MyHDL - which spits out Verilog/VHDL but is programmed in python and its consistent modelling removes some of the problems with Verliog and VHDL as languages. ? - http://en.wikipedia.org/wiki/MyHDL - http://www.myhdl.org/doku.php - http://www.jandecaluwe.com/hdldesign/ - specifically http://www.jandecaluwe.com/hdldesign/the-case-for-a-better-hdl.html Articles/examples: - http://www.linuxjournal.com/node/7542/print - http://www.fpgarelated.com/showarticle/25.php Can it be used alongside, or integrated with, your Papilio Schematic Editor ? Maybe this could help to get people learning and contributing some modules and lighten the load ?
  7. Neon22

    The next generation Papilio - help me shape it.

    Couple of unrelated issues: Great idea about using fpga to create 'circuits' attached to Arduino as a stepping stone.Related KS was FreeSOC - which can be configured with various 'circuits' and is a kind of middle ground of this idea.I do not know how pickup has been after initial KS... perhaps you could ask him ?http://freesoc.myshopify.com/products/freesoc-development-kitInstead of unpopulated BGA area for SDRAM - how about an unpopulated SO-DIMM laptop RAM connector ?http://en.wikipedia.org/wiki/SO-DIMMThe vortex86 has a cute arduino add-on with a breadboard attached. The breadboard can help with connecting devices like PMOD etc. Just an idea for form factor.- http://shop.dmp.com.tw/INT/products/24
  8. Neon22

    Quadrature encoders and LCD

    Hi Jack, Yes I see your point. While I am familiar with s/w design as well as h/w and circuits - I am not familiar with this change in thinking required to go from regular s/w design to h/w. It seems to all be about clock edges. Do you know of any article which tries to setup how to make the change in thinking from s/w programming to FPGA stye prgramming ?
  9. Neon22

    Quadrature encoders and LCD

    Jack - how do you feel about the python myHDL tool for this. I'm feeling daunted by native verilog and vhdl... http://www.myhdl.org/doku.php/start
  10. Neon22

    Williams Defender

    IIRC this used some custom mods on a Jamma board. Mainly the sound unit was separate and had its own distinctive samples. I'm not sure about the rest.... Based on a 6800 and had 320x256 screen http://en.wikipedia.org/wiki/Defender_%28video_game%29 Has Anyone attempted a Defenders port ? Defender, Williams Electronics, 1980 - Arcade by www.diyromarcade.com, on Flickr