ivanjh

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Everything posted by ivanjh

  1. ivanjh

    Pipistrello - "Papilio on steroids"

    Yeah, a packet of matches and a metric shit-tonne of patience.
  2. ivanjh

    Pipistrello - "Papilio on steroids"

    Jack, when you say "boards" (talking about manufacturing costs), you're talking about assembly right? I ask as the "quote for this board was $450 for 50 boards" sounds quite affordable to home-hackers if you're ready to spend a dozen weeknights with tweezers, balls, a skillet and test probes for one working board. I'm a complete novice, and just curious. Is there more difficulty in placing BGA devices? Testing? Re-replacing costs? The devices come "pre-balled" right? You did some BGA assembly yourself... Which bit is the hard bit?
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  4. ivanjh

    Building ZPUino HDL

    I've grabbed the most recent ZPUino HDL and tried to build it "all". https://github.com/a...abd3b8a95876fcd Basically I tried to build every Makefile under "zpu/hdl/zpuino/boards" for i in `find /mnt/scratch/ZPUino-HDL/zpu/hdl/zpuino/boards/ -name Makefile -printf %h\\\\n`; do cd $i make | tee $i/Makefile.out done A number of the makes failed. https://raw.github.c...00/Makefile.out https://raw.github.c...16/Makefile.out https://raw.github.c...on/Makefile.out Are we expecting failures in these makes, or is it something about my setup?
  5. ivanjh

    Building ZPUino HDL

    I would guess either Alvie's or GadgetFactory's Git repos... https://github.com/GadgetFactory/ZPUino-HDL/tree/master/zpu/hdl/zpuino https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/hdl/zpuinoBut I'm not sure any particular versions or builds are tagged.
  6. ivanjh

    Building ZPUino HDL

    Hmm.... I have not downloaded bit files - I've always built mine from source. So, I'm not even sure where you've gotten the ones you've got. Where did you get these bitfiles from?
  7. ivanjh

    Zpuino GPIO speed

    I think the "Alpha 4" is quite an old iteration, and that comment mightn't be relevant to current code. That being said... I did a little checking. It looks like zpuino_io instantiates a zpuino_intr (interrupt controller) with INTERRUPT_LINES => 18 The interrupts are on signal "ivecs" (17 downto 0); It then maps the 16 slot interrupts onto "ivecs" (0 to 15). That does leave 2 interrupt lines "dangling around". In fact, if you check the build log, you'll see: WARNING:Xst:653 - Signal <ivecs<17:16>> is used but never assigned. This sourceless signal will be automatically connected to value 00. That's confirmation that those extra interrupts aren't connected anywhere, and would be optimized away in the actual bitfile. So, you could use them... but you'd need to mod the VHDL and synth your own bitfile. But if you're making your own... you wouldn't need to rely on those two - as you could just hook the ones exposed for the wishbone bus.
  8. ivanjh

    Zpuino GPIO speed

    Hmm... I don't think the standard zpuino has external interrupt support. You may have to create your own customised zpuino to achieve this. If you're not familiar with VHDL, learning to do this will take some learning (~dozens of hours).
  9. ivanjh

    Ultimating 1.0 release.

    Try the manual for a good peripheral overview - http://www.alvie.com/zpuino/downloads/zpuino-1.0.pdf Hmm... there's no i2c mentioned.
  10. ivanjh

    Building ZPUino HDL

    Sweetness & light. ;-) Nice work. Looks like only the nexys3_S6LX16 & the papilio-plus_S6LX4 don't Make nicely at the moment. build.fail.nexys3_S6LX16.log - ERROR:HDLCompiler:636 - "/mnt/scratch/ZPUino-HDL/zpu/hdl/zpuino/boards/nexys3/S6LX16/nexys3_top.vhd" Line 365: Net <gpio_o[52]> is already driven by input port <I>. https://raw.github.c...xys3_S6LX16.log build.fail.papilio-plus_S6LX4.log - Seems to be a problem building the bootloader. ../common/register.h:9:33: board_papilio_plus.h: No such file or directory https://raw.github.c...-plus_S6LX4.log My current logs (and build output) @ https://github.com/i...-HDL/tree/build
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  12. ivanjh

    Building ZPUino HDL

    *sigh* Except that I did mess up, and add a dupe. https://github.com/ivanjh/ZPUino-HDL/commit/26310eb017200532f88bba49490e10a6d514e55f There's still some issues stopping /papilio_one/s3e500/variants/hyperion/ from building Compiling vhdl file "/mnt/scratch/ZPUino-HDL/zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/hyperion/../../../../../wb_char_ram_8x8_sp.vhd" in Library work. ERROR:HDLParsers:3264 - Can't read file "/mnt/scratch/ZPUino-HDL/zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/hyperion/../../../../../wb_char_ram_8x8_sp.vhd": No such file or directory When I sort it out, and get it to build, I'll send another pull request. Also the / zpu / hdl / zpuino / boards / papilio_one / s3e500 / variants / apollo seems to missing it's PRJ file. Did it get forgotten, or doesn't really exist yet? P.S. At the moment, my latest build logs are at: https://github.com/ivanjh/ZPUino-HDL/tree/build built from my https://github.com/ivanjh/ZPUino-HDL/commits/pullreq fork.
  13. ivanjh

    Starting with FPGA

    If this is your one experimental board... I'd suggest the 500K. For most beginner "production" purposes, the 250K would be fine. But if you're wanting to experiment and learn... the 500K will allow you to try things that the 250K couldn't hold. To replace an Arduino Plant Watering System - 250K To learn and experiment with - 500K Get the 500K
  14. ivanjh

    Building ZPUino HDL

    Are you happy to accept GitHub pull requests? Or do you prefer another method for proposed changes?
  15. ivanjh

    Starting with FPGA

    I was new do this (I still am), and got myself a Papilio. The difference? In standard embedded, you *buy* logic, in FPGA you *design* logic. Wish your AVR chip had 48 PWM channels? With an FPGA, you can create an AVR core linked to 48 PWM channels! Everything I learned, was from searches on the net. There's some good material out there... you'll find great stuff on EDU domain sites (looks crappy - 1990s web - but the content is very good). Unfortunately, I can't remember any off the top of my head - Google is your friend. The material at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_course is a pretty good launch point.
  16. ivanjh

    Building ZPUino HDL

    Looks like the new drop breaks a few things: ERROR:HDLParsers:3312 - "/mnt/scratch/ZPUino-HDL/zpu/hdl/zpuino/zpuino_intr.vhd" Line 194. Undefined symbol 'Undefined'. https://raw.github.c...kefile.fail.out It appears that "Undefined" was introduced in: https://github.com/a...80f213dc0f64c7b But seems to be missing from most of the board "zpu_config.vhd"s https://github.com/a.../zpu_config.vhd Or... it could be me... I've tried to drop my make logs here (WARNING - not very stable at the moment): https://github.com/ivanjh/ZPUino-HDL/tree/build
  17. ivanjh

    Building ZPUino HDL

    Oh, I was just going to start playing with a few things, and wanted to make sure I didn't break any interdependencies. Some didn't build, and since I'm quite new to this, I wasn't sure if it was my setup - or a real build problem. (I've had all sorts of fun getting ISE to run - glibc crashing craziness ) Synthesizing all of the boards is really just a sanity check for me, I wasn't harassing you for a fix.
  18. Hmm, this is something I started myself a while ago. One of the problems with extending the AVR softcore is that it just didn't seem to be built for a peripheral rich setup (IO space, etc). But I didn't want to leave an open source GCC based solution. Which is why I've watched the ZPU work with interest. I recently tried to use a quadrature interface from opencores, but it was far too featureful and resource heavy. So instead, I created my own "simple" quadrature interface for the ZPU, and using the standard HD44780 code in the ZPUino IDE install, created a sketch to read the quad counter and write to the LCD. It is so very nice to read a quadrature encoder as simply as: unsigned int y=REGISTER ( IO_SLOT (8) ,0); Serial.println(y); And to know that it is being clocked at 96Mhz. (Of course, I most probably have created a piece of junk, full of bugs - but I think it's cute) The code's a complete mess, but if you're interested... it's attached. View attachment: ZpuQuadDec.zip
  19. ivanjh

    Quadrature encoders and LCD

    Hmm, this is something I started myself a while ago. One of the problems with extending the AVR softcore is that it just didn't seem to be built for a peripheral rich setup (IO space, etc). But I didn't want to leave an open source GCC based solution. Which is why I've watched the ZPU work with interest. I recently tried to use a quadrature interface from opencores, but it was far too featureful and resource heavy. So instead, I created my own "simple" quadrature interface for the ZPU, and using the standard HD44780 code in the ZPUino IDE install, created a sketch to read the quad counter and write to the LCD. It is so very nice to read a quadrature encoder as simply as: unsigned int y=REGISTER ( IO_SLOT (8) ,0); Serial.println(y); And to know that it is being clocked at 96Mhz. (Of course, I most probably have created a piece of junk, full of bugs - but I think it's cute) The code's a complete mess, but if you're interested... it's attached. This post has been promoted to an article