Zvonimir

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Everything posted by Zvonimir

  1. Zvonimir

    Shifty AVR8 + custom core

    Jack, thanks! Beiing a noob, I messed up a source code file that I did not change, as I was exploring them. Some of them I kept chaging, then reverted them back etc. But good documentation is really needed for this kind of stuff, otherwise it gets hard to use. I am proud You merged it in - keep me in the loop if somebody reports something else broken, which it really should not. I shipped this solution internally in my company and it is being used actively and seems to work. ;-) Thanks - Zvonimir
  2. Zvonimir

    Shifty AVR8 + custom core

    Hi, I got Shifty AVR to work great with custom core; also in the same process, I have added SPI and pin shifting ability to Vanilla. I wonder if it would be useful to upload the new Shifty design - with 16 bit I/O addressing and custom core example? I will check if I can sign up somewhere... THANK YOU VERY MUCH. Zvonimir
  3. Hi, I have followed a AVR8 custom core tutorial and have successfully synthesized custom core, same as in tutorial, starting from version 1.6. However, if I try to use sdfat.h and sdfatutil.h libraries, in my sketch, they do not work - I do not even get an error, I just hang on first card.init. (I made sure to select "custom" in Arduino IDE). I tried all exemplary SD sketches and all have the same problem. Just out of curiosity, I printed on serial port value of SPI_miso_LOC and it is 0, which is not right, according to AL assignment. I also tried to just synthesize AVR8, without any custom core, and I get same results. If I use "AVR8_PapilioOne_500.bit" from the bitstreams, then I get it to work. Does anybody know what am I doing wrong? THANKS! Zvonimir
  4. Done - I just committed to Github and sent You a pull request. Detailed documentation is provided in the trunk, and I can add more to clarify any issues remaining. BR, Zvonimir
  5. Zvonimir

    Shifty AVR8 + custom core

    Jack - hi - I have forked the AVR8 soft core design from the Github, and uploaded my branch, and sent You a pull request, as we discussed back in June (could not find that post though - it is somehow gone...). Anyway, check it out, and let me know. I tried to add detailed documentation in the docx and PDF files, as the changes look too scary in Github diff view.Thanks - Zvonimir
  6. Zvonimir

    Quadrature encoders and LCD

    K., sounds like a fun project to start with. See my comments inline
  7. Zvonimir

    What Software to download

    K, Xilinx ISE is Your best choice in so many ways. Gadgetfactory and papilio.cc support Papilio dev with a lot of great tutorials and code samples, all implemented, debugged and simulated using Xilinx ISE. So, the download is definitively worth the trip to some (faster) WiFi hotspot. Additionally, many actual pros use the same tool, so You are getting a top notch training along the way. BR, Z.
  8. Jack - great! I will get cranking then over the weekend! I am proud to be part of the community. Z.
  9. Hi, I got Shifty AVR to work great with custom core; also in the same process, I have added SPI and pin shifting ability to Vanilla. The ISIM debugging was key to figuring out what was going wrong - I was able to see that iowe was not behaving as it should, which I manage to trace to pm_fetch_dec and swap_pins! The problem was on how pin swapping was implemented - I had to change constant const_ram_to_io_c in pm_fetch_dec to "0010" and use memory space from 2000 in the custom core - this has resolved all the conflicts in 0x1000 - 0x1FFFF portion of memory space that I had. I wonder if it would be useful to upload the new Shifty design - with 16 bit I/O addressing and custom core example? I will check if I can sign up somewhere... THANK YOU VERY MUCH FOR YOUR HELP! Zvonimir
  10. Jack, a minor update. I managed to add custom core to Shifty, and have reached an interesting point, certainly an improvement, by doing debugging with AVR simulator and ISim simulator. In general, I can get either my custom core to work, but not SPI, or to have SPI core to work, but not the custom. All the changes that make the difference seem to be isolated now in pm_fetch_dec.vhd. I think there is some conflict between IO and memory mapping that I have to chase down...I am curious if You have any comments. Thanks! Zvonimir
  11. Zvonimir

    AtmelStudio 6 and ATmega103 support

    Hi, here is the final observation. I have installed AVR Studio 4 in Windows XP SP2 virtual machine (by VMWare) and ran the same ELF file, as in ATMEL Studio 6 (but there with AVR Simulator using ATmega128 model, as ATMega103 is not supported any more since version 5). If you really want AVR studio 4, and are already running Windows 7 or later, I recommend building VM in VirtualBox or VMWare, as compatibility mode seems not to work at all. But regarding using ATMel Studio 6, it seems so far that there is a great deal of compatibility between ATMega103 and ATMega128 instructions set, as the disassembler appears substantially similar from what I can see. Here is the output from AVRStudio4: +0000004D: 07B1 CPC R27,R17 Compare with carry +0000004E: F7E1 BRNE PC-0x03 Branch if not equal +0000004F: 940E005A CALL 0x0000005A Call subroutine +00000051: 940C00C0 JMP 0x000000C0 Jump +00000053: 940C0000 JMP 0x00000000 Jump @00000055: setup ---- C:\Documents and Settings\Administrator\Local Settings\Temp\build887447173438038686.tmp\AVR8_Custom_User_Core_5_DEBUGONLY_Shifty_TAR.cpp 23: void setup() +00000055: E083 LDI R24,0x03 Load immediate +00000056: 93801010 STS 0x1010,R24 Store direct to data space 27: } +00000058: 9508 RET Subroutine return @00000059: loop 29: void loop() +00000059: 9508 RET Subroutine return @0000005A: main ---- C:\Program Files\Papilio-ArduinoIDE0018f\hardware\arduino\cores\arduino\main.cpp ------------- 5: int main(void) +0000005A: 940E00A9 CALL 0x000000A9 Call subroutine 9: setup(); +0000005C: 940E0055 CALL 0x00000055 Call subroutine 12: loop(); +0000005E: 940E0059 CALL 0x00000059 Call subroutine +00000060: CFFD RJMP PC-0x0002 Relative jump @00000061: __vector_16 ---- C:\Program Files\Papilio-ArduinoIDE0018f\hardware\arduino\cores\arduino\wiring.c ------------- 45: { +00000061: 921F PUSH R1 Push register on stack +00000062: 920F PUSH R0 Push register on stack +00000063: B60F IN R0,0x3F In from I/O locationHere is the same output for ATMel studio 6, using ATmega128 in simulator: 0000004D b1.07 CPC R27,R17 Compare with carry 0000004E e1.f7 BRNE PC-0x03 Branch if not equal 0000004F 0e.94.5a.00 CALL 0x0000005A Call subroutine 00000051 0c.94.c0.00 JMP 0x000000C0 Jump 00000053 0c.94.00.00 JMP 0x00000000 Jump --- C:\Users\ZSDSA0~1\AppData\Local\Temp\build190981914504925258.tmp/AVR8_Custom_User_Core_5_DEBUGONLY_Shifty_TAR.cpp 23: void setup() 24: { 25: customCoreControl = 0x3; 00000055 83.e0 LDI R24,0x03 Load immediate 00000056 80.93.10.10 STS 0x1010,R24 Store direct to data space 27: } 00000058 08.95 RET Subroutine return 35: } 00000059 08.95 RET Subroutine return --- C:\Program Files\Papilio-ArduinoIDE0018f\hardware\arduino\cores\arduino/main.cpp 5: int main(void) 6: { 7: init(); 0000005A 0e.94.a9.00 CALL 0x000000A9 Call subroutine 9: setup(); 0000005C 0e.94.55.00 CALL 0x00000055 Call subroutine 12: loop(); 0000005E 0e.94.59.00 CALL 0x00000059 Call subroutine 00000060 fd.cf RJMP PC-0x0002 Relative jump --- C:\Program Files\Papilio-ArduinoIDE0018f\hardware\arduino\cores\arduino/wiring.c 45: { 00000061 1f.92 PUSH R1 Push register on stack 00000062 0f.92 PUSH R0 Push register on stack 00000063 0f.b6 IN R0,0x3F In from I/O location Again, this is not too surprising, although I am not sure if in some debugging case it would be bad to rely on ATmel studio 6 and ATMega128...If YOu have any suspicions, make sure to try AVR Studio 4 on a Win XP VM. Best regards, Zvonimir
  12. Hi, if anyone recently played with AVR Simulatior/debugging and ATMelStudio6 and figured out what to do with support for Atmega103? Atmega103 is not supported any more, and I am wondering if I should downgrade to version 5, or there is a XML device file for ATMega103 somewhere? thanks! Zvonimir
  13. Zvonimir

    AtmelStudio 6 and ATmega103 support

    Jack, correct, and then with the older simulator version 4, You have to get Windows XP machine, at least Windows 7 or compatibility modes are a no-go. Although, if I choose Atmega128 as a device, I seem to get correct disassembly at least for your tutorial example (unfortunately by the spec, atmega128 and atmega103 have a lot of differences, so this is not a solution). Z.
  14. Zvonimir

    AtmelStudio 6 and ATmega103 support

    Ok - for those who search this kind of stuff later, even Atmel studio 5 is not supporting atmega103; so I am downloading AVR studio 4, which obviously does support it (from Jack's tutorial). There could be slight Windows 7 incompatibility,we will see.
  15. Jack, yes, I certainly found the page, and started working on tutorial. So far my FPGA debugging was strictly based on debugging VHDL, after which usually everything worked. I downloaded ATMEL studio last night, and went through 1/2 of the tutorial. I will let You know how things progress. thanks! Zvonimir
  16. Minor update: I moved SPImaster to Vanilla. It generates bitstream nicely, but unfortunately does not work. I am reading the articles on simulation to see how to debug this thing... Zvonimir
  17. Jack, thanks for the advice...but, unfortunately I spent last two days doing the wrong thing, i.e. I wanted to add my custom core to the Shifty. I immediately got into 6-bit addressing vs. 16-bit addressing conflict, which I managed to resolve, by carefully chasing 6-bit addresses and comparing to what Vanilla has. I got it to the point where Shifty actually works correctly, albeit my custom core is not. I am not sure what exactly went wrong - I think I got myself in a corner, where some of those warnings I am getting during the bitstream generation are actually important... If I set porta and portb to FALSE (and do not touch DDRAreg and DDRBreg), everything compiles, but porta and b (which I use for custom core inputs/outputs) seem to be dead on the actual board. If I let porta and b TRUE (and use DDRAreg and DDRBreg to set pins as inputs), then I get conflicts with shifting functionality. Finally, I need about 16 addresses in the memory space, and I am not sure what is all used by Shifty - seems that starting at x0FE0 (like in Vanilla custom) is bad, as that collides with PWM and SPI registers (I can see it in pins_papilio.c), so I moved to x0FF0 and used 16 addresses thereafter, but didn't seem to make much difference. My hope was to make You happy with Shifty working with custom core, which probably would be useful to all the folks interested in customization...if nothing, I have working shifty with 16-bit addressing through and through. I look forward to whatever you have with adding SPI to Vanilla. I can try to do it in parallel, or, if You want me to, I can act as a tester etc. Thank You very much! regards, Zvonimir
  18. Jack, OK - I got shifty AVR8 ver 26 from the SVN, and got it to synthesize on its own, and core is working with sdfat libraries, as expected. I am not sure now which one will be easier to me - as a nubie - to add my custom peripheral to shifty, or to figure out SPI manually in Vanilla with the customized peripheral. If You have an opinion, let me know. Thank You very much! Zvonimir The version that is included by default with the Papilio IDE is the "Shifty" variant which includes the SPI master and the code to move pins on the fly. The version that is used in the custom core tutorial is the "Vanilla" variant which does not have the SPI master integrated yet and does not have the code to move pins. The thinking is that the pin shifting code is very expensive and ends up using 99% of the P1 250K and if you are making a custom core you can specify where the SPI pins connect manually and save a TON of space. Integrating the SPI master into the "Vanilla" variant is on my task list but has not been completed yet. It should be easy to look at the "Shifty" variant and do the same thing in the "Vanilla" variant and add constants to control whether it is synthesized or not. Jack.
  19. Jack, hmm - how embarassing for me. I thought I was using "shifty" branch. I actually found this paragraph You quoted, and I assumed that the version I was using was shifty. I will search for "shifty" version of the VHDL and report tomorrow what I got, after I get it from SVN. Is there an explanation/manual then how to set up SPI to work with Vanilla version? Thank You very much! Zvonimir