vhdlnerd

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About vhdlnerd

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  1. vhdlnerd

    Help with ZPUino and PapilioPlus

    Jack, I think I'll take you up on the trade. I'll email for the details Thanks, -vn
  2. vhdlnerd

    Help with ZPUino and PapilioPlus

    Jack, But, will that help much with my Papillo Plus board? Is there anyway to tell if ZPUino is running on my board before the IDE tries to download to it. Should the LED be blinking or is there one of the I/O pins toggling. I tried rebuilding the ZPUino bit file from the source (at github) -- I only saw a Plus lx4 board directory. I modded the source for a LX9 device. However, the build I created still would not "talk" to the zpuinoprogrammer.exe program. Thanks again for the help, -vn
  3. vhdlnerd

    Help with ZPUino and PapilioPlus

    Still no joy! I still don't see a board option for a PapilioPlus LX9 in the IDE (just the Pro version). I tried adding this to the boards.txt file: zpuino_papilio_pluslx9v.name=ZPUino on Papilio Plus (LX9) zpuino_papilio_pluslx9v.upload.protocol=zpuino-serial zpuino_papilio_pluslx9v.upload.maximum_size=12160 zpuino_papilio_pluslx9v.upload.size_sections=all zpuino_papilio_pluslx9v.upload.speed=115200 zpuino_papilio_pluslx9v.build.f_cpu=96000000L zpuino_papilio_pluslx9v.build.core=zpuino zpuino_papilio_pluslx9v.build.toolchain=zpu zpuino_papilio_pluslx9v.build.extraCflags=-D__ZPUINO_PAPILIO_PLUS__ -DBOARD_ID=0xA4040F00 -DBOARD_MEMORYSIZE=0x8000 -nostartfiles zpuino_papilio_pluslx9v.build.extraSflags=-DBOARD_ID=0xA4040F00 I got the board ID number from the ZPUino HDL GIT area and I think the RAM is 2x the LX4 version (read it in a text file somewhere). But, still no joy. I'm using this bit file: zpuino-1.0-PapilioPlus-S6LX9.bit from the ZPUino Web page download area. I'm guessing I don't have the correct bit file or the board definition in the arduino is not correct. Thanks again for the help. -vn
  4. vhdlnerd

    Help with ZPUino and PapilioPlus

    Thanks, Alvie! I'm downloading now... I'll let you know how it works. -vn
  5. vhdlnerd

    Help with ZPUino and PapilioPlus

    Recently, I finally had time to play with ZPUino. I downloaded the ZPUino IDE (for WIndoze) and got a few sketches working on my P1-250 board. I'm having issues with my Papilio Plus with the LX9. I have the ZPUino bit file for the LX9 downloaded to the board (using the Loader 2.4) and it verifies OK. However, I cannot download compiled sketches via the ZPUino IDE. The zpuinoprogrammer.exe utility just hangs and I eventually have to kill the zpuinoprogrammer.exe process. One thing that could be the issue is that the ZPUino IDE does not have a LX9 board option just a LX4 board. Is there a LX9 board definition I should be using? Thanks for any help! -vn
  6. vhdlnerd

    VN VGA Controller

    I just got a P+ board and I created a new demo of my VGA controller for it. The original thread for the P1 version is here. And, the code for the current demo is on github. There are several pre-built bit files in the project with different VGA resolutions; so, give them a spin and let me know what you think. (You need a VGA wing plugged into A0-A7.) This demo project is a work in progress; I'll be working on it when I have free time. -vn
  7. vhdlnerd

    VN VGA Controller

    I was able to get a Papilio Plus board with the S6 LX9 FPGA. So, I created a new VGA demo using this board and the Arduino Soft Core. Its now a standalone demo. The code, with bit files, can be found on github. I built a Papilio One 500k version (there is a bit file for this in the project) but I don't have this board to test it on. Please, if someone could try this bit file and let me know if it works, I would greatly appreciate it. Since I'm targeting the Papilio Plus board now, I'll continue this thread in that forum. -vn
  8. vhdlnerd

    Bare Bones I2C Master Writer

    Nice coding style indeed! Very clean. One thing you could do to avoid changing the seqT type when you add/remove I2C commands from your constant is define the type as: [tt] type seqT is array(natural range <>) of i2cT;[/tt] then the type is unconstrained and the the constant [tt]seq[/tt] can vary in length. You need to change the index signal to: [tt] signal idxSeq: integer range seq'range;[/tt] and change all the [tt]seqT'low[/tt] to [tt]seq'left[/tt] and the [tt]seqT'high[/tt] to [tt]seq'right[/tt]. I ran your testbench with these changes and it looked like it worked fine. And, it got through XST without error. That's the great thing about VHDL: lots of ways to do the same thing (and its the bad thing about VHDL, also. ;D ). -vn
  9. vhdlnerd

    VN VGA Controller

    I never thought of using the DDR outputs to reduce the internal pixel clock by two -- I might have to play with that. But, I think you are correct, you cannot infer DDR outputs (or inputs) -- at least, not yet. However, creating a high rez VGA display with a high rate pixel clock on these hobby boards is not very useful -- you really only need a 800x600 (or my favorite, 1024x768) pixel display. But, still fun to play with the higher speed stuff for a learning experience! This does remained me: my demo uses the pixel clock for all of the design. It would be better to use a slower clock for the non-VGA stuff. (I already have the DCM code written to generate a second, slower, clock.) Then, this would be an example of a multi-clock design, also. I think I'll work on that next (after I'm dome playing with my CRAM wing). -vn
  10. vhdlnerd

    VN VGA Controller

    I finally have a first cut at the VN VGA controller done. Please, check it out and leave some feedback. A few points: The ISE project targets the P1 250k board (should be easy to change for a P1 500k). A VGA wing needs to be plugged into CH (or move the wing to the port of your choice and update the ucf file). A SPI interface is on the CL port. There is a Arduino sketch that will show off some of the VN VGA features. So, you need to hook up an Ardruino board (or another P1 with an Ardruino compatible softcore) to port CL. See the ucf file for correct hook up. WARNING: If you use a real Ardruino board, it has 5V I/O! Do not hook this directly to your Papilio! You need to use series resistors -- 330 ohms will work. For more info, see Xilinx AR#19146. You only need the resistors on the signals being driven by the Ardruino board (SPI Clk, SPI CS, and SPI Master to slave data). Even without a Ardruino board, you can try out one of the many bit files. By default the demo design will fill the screen with all the characters in the font in green with a black background. So, you can see what the different resolutions/font combos look like. (I think the DIS_1024x768_128x64x256 display type is the nicest -- its a 1024x768 pixel display, using a 8x12 pixel font (with 256 char defined) yielding a 128 column by 64 row text display. This display type uses the BRAMs efficiently and the number of rows & columns are a nice power of two.) The code is on github. There is still a lot I would like to do with the design: [list type=decimal] [*]Make a self-contained demo (no external Ardruino board required). This will require a P1 500k. I don't have one . But, I do have the use of a Spartan 3E eval board, which has the same 500K size FPGA. I might make a new demo with a ARV8 or ZPUino together with my VGA controller and have someone here verify it on their P1 500k board. [*]Add more comments to the code. [*]Add a hardware scroll feature. [*]Support a raw mode and a text mode. Raw mode is what I have implemented so far -- the user must reposition the cursor location a lot to display text on the screen. The new "text mode" would give the user a dumb terminal for output -- where CF, LF, FF characters would be handled and automatic line wrapping & scrolling would be implemented. [*]Add more display types (see the displayPack.vhd file). [*]Add more fonts (see the fontPack.vhd file). [*]Add support of fonts wider than 8 pixels -- could be useful with the higher res displays. [*]Create a Wiki page to explain the design, if there is any interest. [*]Re-target the design for the Papilio Plus board as soon as I get my hands on one . This should take very little effort -- should only need to mod the pixel clock generation code (for DCM differences between the S3E and S6). I'm hoping this is a good example of a scalable design. Please, let me know what you think. (And, let me know if there is anything missing from github -- this is the first time I've used git and github.) -vn
  11. vhdlnerd

    Papilio at SparkFun

    I see you can buy a Papilio One 500k at SparkFun, now. Cool. -vn
  12. vhdlnerd

    VN VGA Controller

    Yes, I looked in the AVR8. Unfortunately, it uses all but two BRAMs on the 250k Papilio One. The VGA controller needs at least four. I guess I should have got a the 500k . -vn
  13. vhdlnerd

    VN VGA Controller

    I figured I'd start a new topic to post the status of my first Papilio One project - a VGA controller. The basic features of the controller are: Targets the 250k Papilio One board (should work in the 500k board, too) Uses the VGA Wing Generates a text display Glorious 3-bit Color Output Hardware Cursor (with selectable style) Completely Scalable Design: The controller can be reconfigured via a few constants Many different VGA resolution standards may be selected (I've tested a few from 640x480 to 1600x1200, already) Different fonts can be selected - fonts can be of different sizes (width and height) - I have three font sets defined currently: one 8x12 and two 8x16 (with 128 or 256 chars in each) All logic and RAMs are inferred -- no Xilinx cores (except for the DCM primitive -- cannot infer that one) (Note: The controller's configuration is static -- you choose one VGA resolution and font in VHDL before implementation.) I'm hoping this will be a good example of how to create a scalable design in VHDL and I plan to create a nice wiki page in the playground for it. Right now I have the core VGA stuff working: VGA signal timing generation and outputting a display of all the font characters repeatedly. This was enough to test how well the core scales to handle a 1600x1200 VGA resolution. This requires a 160MHz pixel clock and I was happy to see I still have some margin for the clock rate (however, I don't have much else in the FPGA; so, it may be hard to meet timing at that speed when the FPGA starts to fill up). I'm thinking about having a final demo design of the VN VGA Controller with a SPI interface so an Arduino board can hook up to it and create a sketch to show off what the controller can do. I'm hoping to have some code to show in a week or two. Since I'm new to this open project thing, I'm learning how git works and setting up something on github. I'll post progress soon , I hope. -vn
  14. vhdlnerd

    CRAM Wing

    Jack, Wow, thanks! I'll send you an email. -vn
  15. vhdlnerd

    CRAM Wing

    Jack, What's the status on the CRAM Wing? I would be interested in buying or building one of those. -vn