Thanks for getting back to me, Jack.
I can just import all of the VHDL as discrete hardware blocks, each with their own inputs and outputs, but I run into a wall when it comes to wiring everything up. I can only guess where everything goes.
Re-creating the clocks shouldn't be too hard.
I just don't have much experience with creating an entire thing in VHDL, as all of my experience is Verilog.
Any ideas on what to do?
If not, I guess i'll just have to use the Xilinx ISE Webpack for everything. I have never used it before.