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  1. fuzzy

    Pipistrello - "Papilio on steroids"

    Any news on this fantastic board ?
  2. fuzzy

    DVI-D output

    Wow great achivement, i saw it on hackaday. You cite the Pipistrello development board in your wiki page and in the hackaday article. I tried to find it with google but i got only links to your page, idem if not worst if i try to use the "Magnus Karlsson" keywords, could you please tell us where did you get that board from or any other hints about it ? Many thanks, fuzzy.
  3. fuzzy

    Yet Another VGA Controller

    Thanks for the info. I was asking myself if it was possible to add bigger ram or at least leave the possibility to add it after purchasing the board (i.e leaving unpopulated pads). What kind of Spartan3A package will the next papilio gen use? I'd like to see a higher number of headers/pins (say twice the current to be sure ). I'm asking because I wanted to try to develop a wing for the current papilio that contains DDR DRAM and the chip to convert a 24bit RGB ttl datastream to LVDS which is needed to for the LCD interface project. I think we need a 16 bit wide data/ 24bit address bus (to address the minimum memory quantity required), Write enable, Read enable, Busy/Ready, Data/Address latch, Data valid, and maybe other signals I forgot. Plus we need another bus 24bit wide and control signals for the lvds chip (i don't think we can use the memory bus) For the current papilio generation is possible to use a 32 bit wing together with a 16 bit wing (or a 48bit wing)? On the website it says no but there are 48 pin so it should be possible.
  4. fuzzy

    Yet Another VGA Controller

    how much ram? because we'll need plenty of it to implement a frame buffer at full color resolution! if my calculation are correct at least 1920x1080x24(bpp)x frame (minimum 2 to use the double buffering technique) = 99532800 bits or 99532800/(8*1024)=12150 or roughly 12 MB per frame. Thanks for the app. note it was very illuminating and if what is says it's correct I belive we could start to prototype the RAM wing even for this generation of papilio. In fact we could try to drive lower res display and make the code scalable for higher res display by using registers to change height, width, ad color depth on the fly from the MCU / MPU or automatically by reading the n. of bits in the imput stream. This will be good for testing the code on the current generation leaving the optimization of the pcb (read track impedance matching mainly) for the next papilio.
  5. fuzzy

    Yet Another VGA Controller

    Yes but I some others display use plain TTL or LVTTL parallel interface i think. I do not know what's the max bitstream rate on Spartan3E but I think it might depends on propagation time and maximum clock ratings. I've found this document that tells "The maximum data rate for the Spartan-3E FPGA is 622 Mbps for the -4 speed grade and 666 Mbps for the -5 speed grade". I hope that is the information you were looking for.
  6. fuzzy

    Yet Another VGA Controller

    Is there anyone interested in collaboration to develop a wing that contains ram and LCD interface instead of VGA? by LCD i mean bare LCD panels from repair laptop services. On eBay are quite cheap and range from small 7-10" to 17-19" and often all that they require is an inverter for backlight, a parallel or lvds interface hardware and data to be fed in with . Of course in not all that easy but there are already some examples and moreover by often having digital parallel (or lvds) interfaces they don't require conversion to analog. Pincount requirements might be an issue on papilio tough.