alvieboy

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Posts posted by alvieboy


  1. Hi,

    Actually ZPUino is not (yet) wishbone compliant.

    Now, regarging the timers you can add as much as you want, most IO space is still free. But remember the two included timers in ZPUino are 16-bit, but they are not able to use an external trigger (however this is rather easy to implement, just tell me if you require it).

    In case you want to extend either the number of timers or the resolution that's also very easy to do.

    Álvaro


  2. Right now, with a few HW additions, ZPUino uses 20% of an S3E500, so there should be enough room for USB host/device (if they don't require too much blockram).

    SRAM would be wonderful, even if we have to deploy some sort of cache to speed up things a bit.


  3. I2C should be quite straightforward to implement.

    Mapping registers directly should not be a good idea, because one is a 8-bit micro, the other one a 32-bit :) You'd lose some interesting stuff like 32-bit SPI reads. However software can be of great help here, and we can virtually map those familiar registers in the real ones.

    USB host (at least for USB1.1) should be very easy to implement, not quite sure about its size though.

    I'll take a look at Reduced MII to see what we can do about that. VGA might be harder, because we have little RAM already (are you planning any 8 or 16 bit external SRAM Wing?)

    Right now I'm improving  bootloader and C startup routines (make them smaller and more efficient) so that we can compile C++ and use out-of-the-box. Might need some changes to toolchain code, not yet sure, but those should not be hard to do either.

    Álvaro


  4. Hi,

    ZPUino, being a SoC, includes some "classical" IO devices, such as UART, SPI and timers. It's a fairly small design however, using (as I write) only 18% of one S3E500. So there is plenty of space to implement other device handlers in hardware.

    One I'm already planning to add is a full USB 1.1 or 2.0 controller core (you'll only need proper transceivers).

    What hardware devices would you like to see on this SoC ?

    Right now we have: 1 UART, 2 SPI, 1 SigmaDelta, 2 16-bit timers (PWM-capable), 1 CRC16, plus 32-bit GPIO and interrupt controller.

    GPIO pins can have special functions, like in most SoC. That's the case for most IO pins on ZPUino.

    Álvaro