alvieboy

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Everything posted by alvieboy

  1. Why 32MHz XTAL?

    Try dual-PLL or dual-DCM. These are values for dual PLL on PPro (Spartan6) Input clk: 32000000.000000Hz, Output clk 95000000.000000Hz Best result: 96000000.000000Hz, error is 1000000.000000Hz PLL Mult=15, Divide=5 Scanning two-PLL approach Best result: 95000000.000000Hz, error is 0.000000Hz Master PLL: Mult=30, Divide=48 (fout=20000000.000000Hz) Slave PLL: Mult=38, Divide=8
  2. Hey guys, I am developing a new CPU (for fun and beyond), which aims to replace the slow ZPU we have been using so far. The new CPU design is coming along very well, and should match and eventually outperform the Xilinx Microblaze in program size, performance (MHz) and implementation size (well, perhaps this one not, let's see). The CPU is 32-bit, RISC-like, with 31 general purpose registers, a zero register, and a few special registers. It's an hybrid of well known CPUs, like Microblaze, ARM, SPARC, and others. All instructions are 16-bit, and can be extended for immediate values. It has 2 to 5 asymmetric ALU, which in certain scenarios allows the CPU to execute two (or more) instructions at the same time. All normal addressing modes are supported. The design uses 3 to 6 pipeline stages, depending on configuration. All branch instructions have delay slots. The objective is to have a fast CPU (something between 100MHz and 166Mhz) , superscalar, and have it fit nicely on a PPro/Papilio One while using the same Wishbone interface as ZPUino does. The current state is: it works in simulation, an assembler/linker is already working, still missing the C/C++ compiler (LLVM), Now... I really need to name it. And this is where I need your advice and help. The best name I found so far is "XThunderCore", or abbreviated, "XTC". What are your ideas ? Can you come up with a better name for it ? Best, Alvie
  3. My assumption is that the design you use only maps the first 512KB, despite having a larger SRAM. This is probably due to HDL code not properly driving the two extra address lines. Jack: can you check the synthesis/map output to see if the two uppermost address lines are actually driven by the HDL code, or just tied to '0' ? Alvie
  4. Hi, You can store anthing you want after address 0x60000 for Papilio Pro and address 0x46000 for Papilio One. ZPUino also uses this area, so you may need to push it a bit further if you intend to use it as well. Alvaro
  5. SDRAM controller for Papilio Pro

    Try my (ZPUino) SDRAM controller. You can find here: https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/hdl/zpuino/memory/sdram It uses pipelined wishbone, so make sure you don't hold STB high after your request has been accepted. Also take a look at the PLL settings for it https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/clkgen.vhd Any issue drop me an email at alvieboy at alvie dot com Alvie
  6. Xilinx ise

    Hi Baggey, As far as I know. Xilinx EULA (End User License Agreement) forbids us from shipping the software, either in physical medium or as a download. That is the main reason you have to download it from Xilinx directly. This is far from optimal, we know, but, aside from something I believe Jack is working on (can you confirm @Jack Gassett?, the only way to get the software. Best, Alvie
  7. SPI MODE0

    Let me take a look at that and I'll get back to you. Probably there's a bug there, I don't recall testing it with non-usual modes (it's also tricy to implement). Alvie
  8. perl -e 'use Math::Trig qw/pi/; foreach my $n(0..2047) { print int(128+100*sin($n*2*pi/2048)), "\n"; }' You should be able to translate this to other languages as well.
  9. Ok let's look at the formula. I have not actually read that part in the manual. For the sine argument it splits the full 2*PI range into 2048 entries - so if "n" on that argument ranges from 0 to 2047, it will yield a sinewave across the full 2*PI (360 degrees). It would probably made more sense to write it as "sine( (n/2048) * (2*PI) ). Assuming you indeed want the 360 degree waveform, The waveform amplitude is given by the "100" value - since the output from sine() will be between -1 and +1, the output range [ of (sine(n*PI()/1024)+1)*100) ] will be from -100 to +100. Since you need to bias the output for 1/2 VCC (it's an 8-bit output, no negative values, hence ranges from 0 to 255, "zero" is depicted by 128) you add the 128 bias. That will make the output range from 128-100=28 to 128+100=228. You can change the amplitude at will between 0 and 127. Exactly how to create the COE file... long time I used such tools. Alvie
  10. Back to Basics

    Just a quick note: Adding ZPUino support for AMBA/APB/AHB[-lite]/AXI is not that difficult, although we may not be 100% compliant in the first stages, due to split address+data phases on some of these protocols - still, mapping between the classic wishbone to APB and pipelined wishbone to AHB-lite should be fairly straightforward. If that eases integration with Vivado, we may as well just move to AMBA buses from the ground up. Alvie
  11. ZPUINO on custom board (Spartan 3)

    I fixed paths (not yet on master) and generated a ZIP export file. Should work... not sure - fails on my side with: INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Care to try ? Your luck may vary... Alvie ZPUino_Papilio_One_250K_V2_blackbox_dist.zip
  12. ZPUINO on custom board (Spartan 3)

    I need to update that project file... I do have a script able to generate the .xise file from the main Makefile/prj. However links are broken since I moved stuff around. Will do ASAP... and fix all variants in the way (I did update the main project/boards ones, not all variants though). Alvie
  13. ZPUINO on custom board (Spartan 3)

    Yes, it's a Xilinx project. You may merge all sources into your own project if you like. However blackboxing the core (which is almost always the same) will decrease synthesis time significantly. Alvie
  14. ZPUINO on custom board (Spartan 3)

    Can you try swapping TXD/RXD in the UCF file ? I recall we had some "misunderstanding" regarding the TX/RX direction. That was a long time ago, though. Alvie
  15. ZPUINO on custom board (Spartan 3)

    Does your board have a "DONE" LED or pin so you can check if the FPGA starts ? Are FTDI/Serial connections the same as in original ? Why does your FPGA have a different ID code ?
  16. Unknown Papilio Board

    This one is still odd. Never saw it. Have you tried a different USB port? Best, Alvie
  17. Don't think it would fit any of the Papilio boards. Perhaps the big Pipistrello, have a chat with Magnus ( @mkarlsson ), he should know better than I do (and he uses Microblaze often). Alvie
  18. Wii Wing/Wii Nunchuck questions

    My Wii Chuck is a Nintendo original and worked with the posted settings, I may need to try your changes so se if it still works. Thanks a lot for testing this and finding a fix! Alvie
  19. Wii Wing/Wii Nunchuck questions

    More interested in the setup sequence. If you can capture that one it should shed some light. I suspect SDA is high-tied to VCC, hence the readings and the I2C ack.
  20. Wii Wing/Wii Nunchuck questions

    This seems to imply your Wii chucks are not properly powered?. I used a small adaptor back when I wrote the support code, and played with it for a whole maker faire (many people did). Do you have any digital scope so we can look at the signals ? Alvie
  21. What is the best way to control RS485?

    GF does not support Zynq at the moment, nor Linux interfacing. But my 2 cents: 1 - flush the write to the GPIO control port. 2 - If you really need control over all lines, write a Linux Kernel Driver for it. Also check documentation for that "modbus" library you are using. Alvie
  22. D/DHDL + Classic Empire on Papilio Pro

    Thanks for your reply, Luís. Yes, I am from Coimbra, but don't go to Lisbon that often (except to fly abroad, and that's more often that I'd wished). Still one question: how do you model sync vs. async resets ? Rather easy in low-level HDL languages, but hard to do even in SystemC (I heard newer versions do support it, but it's an ugly hack in my opinion). Alvie
  23. LCD protocol sniffer and analyser

    It may be possible with an USB3300 transceiver. I have a couple, but unfortunately had no time to put those to work. I may need to in a recent future, I'll let you know. Alvie
  24. D/DHDL + Classic Empire on Papilio Pro

    I read one of your PDF files, and to be honest I have much more questions now than I had before, like: - How do you model different clock domains ? - How do you integrate with hard-IP blocks ? - How do you model multi-cycle operations, like a 5-pipeline multiplier ? If you happen to come by Coimbra you may explain me these in more detail Alvie
  25. RISC-V on Papilio Pro

    Thanks for sharing. I still have to ship your stuff, will do so during this week. Also quite busy over here, but definitely have no connectivity issues I will try your design later, but more interested in the HDL design than in the demo. There's been quite some hype around RISC-V, but to be honest I believe it won't live longer - there are some issues with ISA, and some extensions may not play well with others. Also, MIPS is for sale AFAIK, if they drop the patents it may well be a more serious contender to ARM (I think at least Cavium may have some interest in buying MIPS from Imagination - and Imagination is eager to sell everything due to recent contract changes with Apple) Alvie