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Posts posted by alvieboy

  1. Try dual-PLL or dual-DCM. These are values for dual PLL on PPro (Spartan6)

    Input clk: 32000000.000000Hz, Output clk 95000000.000000Hz

    Best result: 96000000.000000Hz, error is 1000000.000000Hz
            PLL Mult=15, Divide=5

    Scanning two-PLL approach

    Best result: 95000000.000000Hz, error is 0.000000Hz
            Master PLL: Mult=30, Divide=48 (fout=20000000.000000Hz)
            Slave PLL: Mult=38, Divide=8


  2. Try my (ZPUino) SDRAM controller.
    You can find here:

    It uses pipelined wishbone, so make sure you don't hold STB high after your request has been accepted. Also take a look at the PLL settings for it

    Any issue drop me an email at alvieboy at alvie dot com


  3. Hi Baggey,

    As far as I know. Xilinx EULA (End User License Agreement) forbids us from shipping the software, either in physical medium or as a download. That is the main reason you have to download it from Xilinx directly.

    This is far from optimal, we know, but, aside from something I believe Jack is working on (can you confirm @Jack Gassett?, the only way to get the software.





    The suggested formula is "f(n) = int((sine(n*PI()/1024)+1)*100)+128" that, as the texts says, "will give you values between 28 and 228 that you can use".

    Ok let's look at the formula. I have not actually read that part in the manual.

    For the sine argument it splits the full 2*PI range into 2048 entries - so if "n" on that argument ranges from 0 to 2047, it will yield a sinewave across the full 2*PI (360 degrees). It would probably made more sense to write it as "sine( (n/2048) * (2*PI) ). Assuming you indeed want the 360 degree waveform,
    The waveform amplitude is given by the "100" value - since the output from sine() will be between -1 and +1, the output range [ of (sine(n*PI()/1024)+1)*100) ] will be from -100 to +100.
    Since you need to bias the output for 1/2 VCC (it's an 8-bit output, no negative values, hence ranges from 0 to 255, "zero" is depicted by 128) you add the 128 bias. That will make the output range from 128-100=28 to 128+100=228.
    You can change the amplitude at will between 0 and 127.

    Exactly how to create the COE file... long time I used such tools.


  5. Just a quick note: Adding ZPUino support for AMBA/APB/AHB[-lite]/AXI is not that difficult, although we may not be 100% compliant in the first stages, due to split address+data phases on some of these protocols - still, mapping between the classic wishbone to APB and pipelined wishbone to AHB-lite should be fairly straightforward.

    If that eases integration with Vivado, we may as well just move to AMBA buses from the ground up.


  6. 13 minutes ago, Jack Gassett said:

    You need to use make to synthesize the project.

    I need to update that project file...
    I do have a script able to generate the .xise file from the main Makefile/prj. However links are broken since I moved stuff around.

    Will do ASAP... and fix all variants in the way (I did update the main project/boards ones, not all variants though).


  7. On 04/07/2017 at 4:45 PM, mikejohnson said:
    Response incompatible with mask xxxx01
    Invalid chain position 0, position must be less than 0 (but not less than 0).

    This one is still odd. Never saw it. Have you tried a different USB port?



  8. Quote

    "and received the same output values via the serial monitor as when connected to the Papilio Pro. "

    This seems to imply your Wii chucks are not properly powered?. I used a small adaptor back when I wrote the support code, and played with it for a whole maker faire (many people did).
    Do you have any digital scope so we can look at the signals ?


  9. Thanks for your reply, Luís. Yes, I am from Coimbra, but don't go to Lisbon that often (except to fly abroad, and that's more often that I'd wished).

    Still one question: how do you model sync vs. async resets ? Rather easy in low-level HDL languages, but hard to do even in SystemC (I heard newer versions do support it, but it's an ugly hack in my opinion).



  10. Thanks for sharing. I still have to ship your stuff, will do so during this week. Also quite busy over here, but definitely have no connectivity issues :)

    I will try your design later, but more interested in the HDL design than in the demo. There's been quite some hype around RISC-V, but to be honest I believe it won't live longer - there are some issues with ISA, and some extensions may not play well with others. Also, MIPS is for sale AFAIK, if they drop the patents it may well be a more serious contender to ARM (I think at least Cavium may have some interest in buying MIPS from Imagination - and Imagination is eager to sell everything due to recent contract changes with Apple)


  11. it's probably better just to stream it using a serial port at 3Mbit/s. The audio DAC relies on the speaker themselves (their inductance) to perform a low-pass filter, in both Sigma-Delta and PWM outputs. What you hear is probably switching noise and some aliasing. Alternative is for you to design such an analogue filter.

    It can be technically possible to send that data over USB using a simple transceiver and isochronous transfers, but we have not done it before.