alvieboy

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Everything posted by alvieboy

  1. alvieboy

    Unknown Papilio Board

    He should have seen 2 serial ports. Perhaps wrong device ? Or driver issues.
  2. alvieboy

    Serial port issues

    Please, send me an email so I won't forget this. I've most of those libs/apps scattered around my repos.
  3. alvieboy

    ZPUino vs Arduino

    Peripherals are the most standard way, although you can indeed use some "undefined" instructions in CPU. Note that with ZPU it will be very hard to use those instructions. GCC is tricky.
  4. alvieboy

    Material for understanding IOBUF and clock routing

    One thing you can use is the RTL viewer that comes with ISE. It will give you some insight about how the synthesizer understood your "code". The technology viewer, however, will have everything mapped into LUT's and it's rather hard to understand how mapping was done. Alvie
  5. alvieboy

    Using on-board RAM in designs

    Looks good. Let me dwelve into this during weekend. Alvie.
  6. alvieboy

    Using on-board RAM in designs

    Oh, you are using the wrapper ? I was not aware of that. Let me look at you new waveform.
  7. alvieboy

    Using on-board RAM in designs

    Indeed, s_ signals look correct. But... But I don't think you are acessing RAM. I see a 1-cycle delay for reads. So I assume you're not using the RAM model for simulation. And your "model" does not model stalling, so I cannot say what is going on. Stalling will definitely happen, and read delays will exist. On a side note: I am able to do full ZPUino simulations indeed, but they can be tricky. What do you have connected as "slave" for the DMA ? Edit: can you send me the model ?
  8. alvieboy

    Serial port issues

    As I told you, I am able to stream raw audio @3MBit/s to ZPUino, play it, and no drops/errors. Full stream is 44100Hz*16bit*2 = 1.411200Mbit/s, and with some overhead (I use HDLC framing). ZPUino has a 2MByte receive buffer, as long as you do not exceed that, you're OK. I can share that code with you, but note that it uses my SerPro library, and for PC only QT and GLIB versions are available (not Java nor Python). Alvie
  9. alvieboy

    Using on-board RAM in designs

    Can you show me a waveform ?
  10. alvieboy

    XThunderCore is taking shape

    Well, not yet, but not XTC issue. I have a wrong WAD file (I may be able to locate original one). Demo is from a different game version (109 versus 108)!But will be too fast actually: QEMU generates host (x86_64 code in this case) and it will perform quiiite fast. I'll let you posted. I was not to fix this (I'm using DOOM as a really CPU stressing application, in order to catch issues), but I can give it a quick attempt. I had this working once (I actually disabled this check), but it eventually crashed on middle of demo, I suspect due to some incompatibilities in both versions. Alvie
  11. alvieboy

    ZPUino vs Arduino

    ZPU is a stack processor, and stack processors are slow One thing they are bad at is branching, because it can never be predicted (it will be a word in stack, but you don't know which until you execute). Also bad at reloading the stack pointer. Another thing is they are bad for normal compliler integration, which do expect registers to exist (we emulate this behaviour by placing vregs in stack offsets). Adding "1" to a variable (which needs to be in stack) requires quite a few ops: loadsp [variable offset]im 1addstoresp [variable offset]In most register-based architectures, if your variable is a register, it takes a single instruction. Some other also allow adding to a memory location directly. Alvie
  12. alvieboy

    XThunderCore is taking shape

    Ok, I spent a few days working with emulation with QEMU for XThunderCore. Works very well so far. Here's a demo of DOOM runnning inside QEMU. XTC implemented with just a bunch of peripherals (UART, SPI for flash, SPI for SD card, VGA). I can now play with some optimizations at compiler level. Alvie
  13. alvieboy

    Material for understanding IOBUF and clock routing

    Yes, no functional difference at all. However, if you do want to use "counterNext" more than once, it will tell synthesis tool that you want only one adder. Although it may not follow the advice. Not always true. Actually, I find the opposite much more readable and understanding, if you follow some rules/conventions. What I often do is this: -- Inputssignal ina, inb: std_logic;-- outputssignal outa, outb: std_logic;type sync_elements_type is record a: std_logic; b: std_logic;end record;signal r: sync_elements_type;process( clk, r, ina, inb ) variable w: sync_elements_type;begin w := r; -- copy regs into variable if ina=1 then w.a := '1'; -- Synchronous. outa <= '0'; -- Asynchronous outb <= '1'; elsif inb='1' then w.b :='1'; -- Synchronous. outb <= '0'; -- Asynchronous. outa <= '1'; else outa <= '1'; outb <= '1'; end if; if rising_edge(clk) then r <= w; -- Update synchronous elements. end if;end process;Alvie [Edit: it posted before I finished]
  14. alvieboy

    Using on-board RAM in designs

    WE signal is only valid when CYC and STB are asserted. It can stay "undefined" (either 0 or 1) as long as one is not on. In 3-8, no stalling occurs. What is relevant is STB being de-asserted. WE can be asserted because it is ignored (no strobing occurs).
  15. alvieboy

    FreeRTOS on ZPUino

    nilrods: sorry I have not yet had time to get you this info. Will do so in next days. I recall you only need a #define in a "config.h" file, but I need to test this, and I have no much free time these days. Alvie
  16. alvieboy

    ZPUino vs Arduino

    Well, most designs use ZPUino Extreme Core, which is used by 1.0 and 2.0. FMUL16 is a quite dedicaded instruction, which helps if you do fixed-point 16.16, but needs to be instantiated in asm (and cannot be done from within "C" due to how GCC interacts with ZPU). FMUL16 behaves as: uint32_t fmul16(uint32_t lhs, uint32_t rhs){ uint64_t result = (uint64_t)lhs * (uint64_t)rhs; return result >> 16;}Quite useful for some DSP functions (like FFT).
  17. alvieboy

    Serial port issues

    Lukas: you're losing data, because you don't read from serial port fast enough, and usually serial port buffers/FIFOs are small. LM32 is not to blame here. I suggest: * use a thread, with a simple read from serial port, which posts to a memory queue. * another thread reads from there, processes, and outputs. I can help you with that, if you need. Objective is to let read() get data from serial port as much as possible, and defer processing of data.
  18. alvieboy

    Acorn Atom on the Duo

    Are you sure ? Note that there's a strict procedure to put SD cards in SPI mode (and AFAIK it's a mandatory mode), but returning to SD mode will require a power cycle. From SD Physical Layer spec: 7.2.1 Mode Selection and InitializationThe SD Card is powered up in the SD mode. It will enter SPI mode if the CS signal is asserted(negative) during the reception of the reset command (CMD0). If the card recognizes that the SD modeis required it will not respond to the command and remain in the SD mode. If SPI mode is required, thecard will switch to SPI and respond with the SPI mode R1 response.The only way to return to the SD mode is by entering the power cycle. In SPI mode, the SD Cardprotocol state machine in SD mode is not observed. All the SD Card commands supported in SPI modeare always available.I don't make a sense of "if SD mode is required". I assume it's a CMD0 argument. Also, make sure that before using card, you send at least 74 clock cycles with data=1 and card de-selected (CS=1). Alvie
  19. alvieboy

    Material for understanding IOBUF and clock routing

    Ideally the synthesis will infer most of that for you, except on a few cases. The most relevant one is when you have an FF which drives an IO pin, and whose output feeds back to the FPGA logic. When this happens, it's not possible to place the FF in the IO Block directly. One option is to replicate the FF, and indeed if you do force the FF to be in an IOB, it will get replicated: Example: Unit <papilio_pro_top> processed.Replicating register sram_inst/ctrl/r_address_11 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_10 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_9 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_8 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_7 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_6 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_5 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_4 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_3 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_2 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_1 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_address_0 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_bank_1 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/r_bank_0 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/rstate_FSM_FFd8 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/rstate_FSM_FFd7 to handle IOB=TRUE attributeReplicating register sram_inst/ctrl/rstate_FSM_FFd9 to handle IOB=TRUE attributeNow, for clocks: There are two main routing infrastructures inside FPGA. One is a general-purpose, used for data, and another is a fast one, used for clock. The latter does not allow a clock signal to propagate but to clock inputs in the CLBs. Also, not all input pins can drive the IBUFG which feed to the clock routing (or PLL/DCM which will then distribute clock accordingly). For clocks, you really want to instantiate the BUFG. If you use DCM and PLL with feedback, you do want to have a BUFG in the feedback loop. Most of other cases, assumung you have "add IO buffers" selected in the synthesis options, will work correctly. Alvie
  20. alvieboy

    Serial port issues

    I wrote the application for hin to test. If a 0x00 is received it will be written to a file. Alvie
  21. alvieboy

    ZPUino vs Arduino

    No, I did not see it as a criticism Actually, what I find odd is how STM32 performs. It should be more performant. Note that you should not use the clock speed a measurement indicator - all platforms behave differently. This meaning that a 5MHZ CPU is not 5x faster than a 1MHz CPU. Not even with same CPU core. Other factors exist that may limit or improve the overall speed. What we do like to know is how much can you perform, per MHz, and how much power you dissipate per MHz. Easy for microcontrollers/small CPUs, not that easy for big ones. TLB misses in intel architectures can take more than 800 clock cycles to complete (refetching tlb, refetching cache). http://www.7-cpu.com/cpu/IvyBridge.html * RAM Latency = 30 cycles + 53 ns If TLB needs to fetch from RAM, at 3.4GHz (clock period 0.294ns), you have 180 clocks just for latency. Add 3x time latency (one fetch for TLB pointer [may be miss], one fetch for TLB itself [may be miss], one fetch for Cache contents [miss]) .. add transaction delay.... it's huge. We don't realise how slow these things are.... Alvie
  22. alvieboy

    ZPUino vs Arduino

    Oh, and you should use: volatile int m[750]; // a 1500 byte arrayYou're not using the computed values. So compiler might just remove code from there. Also, remember DUO is 8-bit memory wide, so a write is actually 4 writes, and reads 4 reads. Alvie
  23. alvieboy

    ZPUino vs Arduino

    Hmm your numbers do not make any sense. STM32 is, by far, faster than AVR8. ZPU is not that faster, but still fast enough. Plus, you forget a couple of things: Both AVR and STM32 use internal memory, ZPUino uses external SDRAM in most cases, which makes it slower. Also, "int" in AVR8 is a 16-bit, and 32-bit on the other two. ZPUino also does not have D-Cache, so all memory reads/writes need to be performed directly with RAM. I wonder if I can run your tests in my new CPU (XThunderCore). Even without DCACHE, it should perform very well.
  24. alvieboy

    Serial port issues

    We sort of traced this back to the PC application, although it's still not clear why app fails to read stream properly. Alvie
  25. alvieboy

    Using on-board RAM in designs

    Just replied to you. I remebered that I have a wrapper in case you want to use it for now. https://github.com/alvieboy/ZPUino-HDL/blob/work-0200/zpu/hdl/zpuino/wb_master_np_to_slave_p.vhd It's a wrapper for a non-pipelined master to connect to a pipelined slave (like the DMA interface). Alvie