alvieboy

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Everything posted by alvieboy

  1. alvieboy

    USB controller / wing

    That's what I meant by "Add virtual filesystem with a single file, use it as Flash for main SPI". So, yes Will be a cool, novel feature
  2. alvieboy

    USB controller / wing

    Ok, let's do something a bit more interesting. Can you give me a couple of use-cases you'd like implemented for USB ? The idea is to test the robustness of the system (and its performance). Remember we only have 12Mbit, which gives an unidirectional speed of about 8Mbit (half of that if bi-directional). Some use cases that come to mind, as examples: - Add SD card, use USB to present SD card as a generic block device. - Add Wii Chuck wing, present as Mouse - Add virtual filesystem with a single file, use it as Flash for main SPI (like, open the device in windows, drop the bitfile, that's all - you just reprogrammed the FPGA ) - Same as above for sketches: drop a bin file, it will reprogram the sketch only. No audio/video for now, please. That will force me to implement the complex isochronous endpoints Alvie
  3. His errors seem to come from a different part of the HDL, hence me asking for him to post the whole source. Note the source lines in the error messages.
  4. You are doing several mistakes there. Which are your internal signals, and which are your interface signals ? Can you post the whole VHDL file so we can understand ?
  5. Use parenthesis, not square brackets.
  6. alvieboy

    USB controller / wing

    Working under Windows too, with VID/PID from Linux Gadget Serial.
  7. alvieboy

    Hamster's SDRAM_Controller

    No, I did not implement on board (I rarely do until I am pretty much sure it works). I wonder if you can use my own version of that controller, which is the one used by ZPUino. The interface is similar, but it requires an extra clock - I am wondering if this relates to the issue you see in hamster's. I'll show you the dual writes later today. I may happen that your IO blocks are sub-optimal. Can you send me these files too so I can run a timing check ? .ncd file .ngd file .pcf file Alvie
  8. alvieboy

    Hamster's SDRAM_Controller

    First analysis in simulation show first output (through serial port) of ''0x41 0x44 0x43 0x42", "ADCB". Does this match your output ? The SDRAM controller also seems to be writing out data in invalid endianess - I see the initial write of "0x41424344", but reads from this address come out as "0x43444142". The two 16-bit seem to be misaligned. Is this something you changed ? Other issues: - You are writing *twice* to the same address. This is not problematic because controller will be busy on second write, still this is a bad thing to do. - You are waiting for cmd_ready to be '1' before asserting cmd_enable. You should assert cmd_enable as soon you have a command, and keep it asserted while controller does not accept it (ie, keep it asserted with correct cada until cmd_ready is '1'). - Same applies to reads, and you are reading twice from each address, which does not make sense. If you can install GTKWAVE I can send you the simulation output. I am not using your SDRAM simulation model though, I am using my own (which I cannot distribute) Alvie
  9. alvieboy

    Hamster's SDRAM_Controller

    Can you send me a ZIP file with all of your VHDL files to alvieboy @ alvie . com ? (I assume they are "public") Just to ensure I am using the correct versions for the memory controller et. al.
  10. alvieboy

    Hamster's SDRAM_Controller

    Do you have any simulation model we can run to see what is happening ?
  11. Finally at home. So I took some minutes to assemble one of my new wings - a very simple design for ESP8266, so you can use it with Papilio and ZPUino. Software and specialized hardware will be prepared in meantime. If we feel comfortable about this design we will share with you all details. For now, just a bunch of photos:
  12. alvieboy

    First new ESP8266 wing assembled

    Not necessarly worried about throughput, rather connectivity and reliability. But with an IO speed of 80MHz and a very efficient processor at 160MHz you can eventually do interesting things with it. The "biggest" data flow I ever used it for is actually OTA upgrade (using my own method). It's rather quick. What do you have in mind ? I can ship you one of these for a very interesting price, since they are prototypes as of now.
  13. alvieboy

    Hamster's SDRAM_Controller

    Indeed at least one of Hamster's controller does support bursts. I use a variant of it in ZPUino. It supports full 32-bit wide-bursts (yes, I also do not support 16-bit, but that can be changed) and almost-full 32-bit writes (there's a dummy waitstate there I need to remove one of these days). See this post for some details on bursting. http://forum.gadgetfactory.net/index.php?/topic/1894-overview-of-an-sdram-transfer/ Alvie
  14. alvieboy

    Wishbone version of the Sump Blaze Logic Analyzer

    And we were able to do a full simulation of the system, so we can find bugs on it.
  15. alvieboy

    First new ESP8266 wing assembled

    Ok first tests done with new wing: ESP reset - PASSESP reset into programming mode - PASSESP reset into "normal" mode - PASSESP programming through ZPUino - PASSSPI data also seems to be there, so I think no issues will arise.
  16. alvieboy

    First new ESP8266 wing assembled

    The main difference between SPI master/slave relates to who triggers communication. Also slaves must make sure they can feed all data in a timed manner, otherwise you may get a buffer underflow. Note that my idea is to pass TCP/UDP packets to and from ZPUino - these can be quite large.
  17. alvieboy

    IoT Panel - Some pics

    Some pics of my IoT RGB panel board. Took some time to actually take some photos today while assembling one. This is the 9th assembled board. Not final release - I still have to do some modifications (mostly to improve its capabilitites). RGB332 tested OK, perhaps better bitdepth will be possible... working on it. Top view: Xilinx XC2C32 CPLD, in charge of panel control: 3.3 and 1.8 LDO. Caps. Close-up on CPLD. Nice soldering. Thanks Jack to make me go back to Kenston Flux pen. Board top overview, along with stock XC2C32. Bottom view. Passives (mostly caps) and ESP8266 - the heart of the design. And fully assembled board. Some components are optional and not populated. Will be removed in version 1.1. What can it do ? Well, many things.... Let me know if you want to watch some demos. Alvie
  18. alvieboy

    Papilio Pro without SDRAM

    Yes, it's better to assign you a new board ID. What's your current memory size ? Plus, is that a custom board or a real Papilio board ? Just to see if it's better to create a new "Vendor" id.
  19. alvieboy

    Papilio Pro without SDRAM

    Looks like you are adding duplicate buffers. Can you try disabling "Add IO buffers" in Synthesis Options, under Xilinx Specific Options ? Alvie
  20. alvieboy

    First new ESP8266 wing assembled

    Still to decide whether to use ESP as SPI master or SPI slave....
  21. alvieboy

    First new ESP8266 wing assembled

    And before any one asks, yes, I have not yet removed the resistor to the chip antenna.
  22. alvieboy

    Papilio Pro without SDRAM

    Can you send me the generated .ELF file? That sketch looks quite small to me....
  23. alvieboy

    Wishbone version of the Sump Blaze Logic Analyzer

    Wondering if you can simulate the latest version with the provided testbench
  24. alvieboy

    Papilio Pro without SDRAM

    I'll try to sort that out once I get to Portugal again. It's rather hard to simulate this properly over here, so I'll have to perform some regression testing with the board itself. Alvie
  25. Thanks for submitting the issues. A: I was talking about conditionals in C++ code using #ifdef blocks. In ZPUino you can put a "config.h" file in the sketchfolder with the defines, and that gets included by "Arduino.h" if present. This is something quite difficult to do with regular arduino code. Since most code uses "Arduino.h" your defines will be applied to all of your code. B:Definitely an interesting idea. Should work ok with 16-bit per pixel. If you combine that with some sort of write-combine cache it should give interesting results. Perhaps even more interesting would be texture mapping, which is not difficult from HW perspective (just use fixed-point calculations). Anti-aliasing might be interesting for vectors (like lines) but it's probably too complex (or better, will use quite some resources on FPGA).