alvieboy

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Everything posted by alvieboy

  1. alvieboy

    USB controller / wing

    We can add a RC if needed, just to raise it slowly during startup if needed. My SDRAM controller does not at use CKE at all, but the pin may have been ground when the board powers up. I guess we can do some testing first.
  2. alvieboy

    USB controller / wing

    +1: get rid of SDRAM CKE. We always tie that to '1'. +2: get rid of LED
  3. alvieboy

    USB controller / wing

    I already know how to do that. But remember the initial plan is to support a HS phy instead like USB3300 (UTMI+/ULPI interface). Once we get it working with my prototype I think we can evaluate switching to 480Mbit, and also OTG support. I think you will need 12 pins for that one, though. Perhaps we can use some of the JTAG/CONF pins too?
  4. alvieboy

    USB controller / wing

    Ok here's a bundle. It uses the previous USB and MTP libraries. HDL: http://alvie.com/files/papilio_pro_dist-ov7670.zip Sketch: http://alvie.com/files/ov7670-demo.zip JPEG lib (replace the old version shipped with ZPUino): http://alvie.com/files/zpuino-jpeglib9b.zip Check the toplevel file for hints regarding camera connection. The USB wing goes into Wing-C low (0-7). If you manage to get it running I'll send you more details on how to associate the Windows driver. Alvie
  5. alvieboy

    USB controller / wing

    Libraries: USB - http://alvie.com/files/zpuino-library-usb-1.0.zip MTP (uses USB) - http://alvie.com/files/zpuino-library-mtp-1.0.zip
  6. alvieboy

    USB controller / wing

    Here's the schematic and PCB for the wing. http://alvie.com/files/usbwing_v1.zip USB controller VHDL (snapshot while I prepare stuff for github push): http://alvie.com/files/usbctrl-d86641-f1666.zip I'll post sketches afterwards after I retest them. Any one interested on the OV7670 controller+USB ? I can share that one too.
  7. alvieboy

    USB controller / wing

    The hardware:
  8. alvieboy

    USB controller / wing

    I'm awful at demos.... What is going on on that video ? 1- am connecting to Papilio Pro FTDI serial port (COM4), as usual. 2- Resetting the FPGA, using the BREAK. 3- Pressing ENTER twice, so twice magic happens.... 4- Connecting the USB wing to Windows (on this case, through virtualbox) 5- Opening the device.... 6- Yes, that's me, live JPEG compression done with ZPUino, pure software. RAW image also available (600K size) - look at how much time it takes to transfer it Was not able yet to get notifications to work, so if I capture more images, windows does not refresh the list. Will look at that with more detail on next few days. Alvie
  9. alvieboy

    Problem between AVR and FPGA

    Exellent to hear that. And we'll be here to support you on your efforts, just yell if you need more help. Alvie
  10. alvieboy

    BitCoin Miner Library

    Yeah, we should be able to speed it up allright
  11. alvieboy

    Problem between AVR and FPGA

    Care to share your VHDL code ? Yes, the signals are quite stable, so you should not see any "bouncing". You are not using Open-Drain on AVR side, right ? You're driving them directly to '1' or '0'. Alvie
  12. alvieboy

    Problem between AVR and FPGA

    Well, you seem to have misunderstood that article a bit. What he refers to is how to capture a transition on an input signal (usually a control signal), like the "strobe" example. These signals are not clocks, and should not be used like clocks. Indeed that is the correct way to do it (and what we do btw in many devices - and what we do (the resync part) on every papilio pin [see pad.vhd for details]. On the contrary, the SPI SCK signal is a clock, and as such it is routed directly inside the FPGA fabric and drives the required logic. It could be oversampled, but that would cost much more resources because you'd have to resync also the MOSI signal. Could have the advantage of not requirign other clock-crossing, but would limit its speed to ~25Mhz (you should do at least a 4x oversample on the signal). Alvie
  13. alvieboy

    Problem between AVR and FPGA

    I'm sorry, where is "spiwb" using edges on a non-clock signal ? How did you reach that conclusion ? Here's the top level instantiation on Papilio Duo. You can see clock is assigned to WING_A(13): spiwb_inst: spiwb port map ( nCS => WING_A(10), --AVR_nCS, SCK => WING_A(13), --AVR_SCK, MOSI => WING_A(11), --AVR_MOSI, MISO => avrspimiso, --WING_A(12), --AVR_MISO, MISOTRIS => avrspimisotris,--WING_A(12), --AVR_MISO, clk => sysclk, rst => sysrst, Here's the PAR report for the Papilio Duo. As you can see the clock is there. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | sysclk | BUFGMUX_X2Y2| No | 860 | 0.751 | 2.142 | +---------------------+--------------+------+------+------------+-------------+ | WING_A_13_BUFGP | BUFGMUX_X2Y1| No | 38 | 0.730 | 2.132 | +---------------------+--------------+------+------+------------+-------------+ | sysclk_sram_we | BUFGMUX_X3Y13| No | 1 | 0.000 | 2.065 | +---------------------+--------------+------+------+------------+-------------+ Alvie
  14. alvieboy

    USB controller / wing

    Heh... you won't believe about next one, once I get it working (not USB blocking the actual demo though). Let me say just that it may include a lens.
  15. alvieboy

    Problem between AVR and FPGA

    The only "filtering" done is clock domain crossing. You should be fine with this up to 100Mhz. There are quite a few docs and pages about CDC, here are some: https://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf http://www.eetimes.com/document.asp?doc_id=1276114 Alvie
  16. alvieboy

    implementing a new wishbone slot

    Hi, I just took a quick look, and that "sel" signal is only one bit wide, and must be tied to '1'. That signal does not make sense at all - the SEL signal is used for byte-access, which the device does not support (ZPUino also does not support it for devices). This design also uses CTI and BTE. You should hardcode them to all zeroes. Regarding documentation, you have the official Wishbone doc, but its a bit hard to follow... Alvie
  17. alvieboy

    USB controller / wing

    Ok, here's an example sketch that allows you to expose the FPGA firmware in SPI flash to PC. #include "mtp.h" #include "spiflash.h" using namespace ZPUino; static SPIFlash_class SPIFlash; class MyMTP: public MTPUSBDevice_class { protected: int getNumHandles() { return 1; } const char *getFilename(int object) { return "spartan6.bin"; } const char *getTimeCreated(int object) { return "20160101T000000Z"; } const char *getTimeModified(int object) { return "20160101T000000Z"; } unsigned getFilesize(int object) { return 340884; } void readObject(unsigned object, uint8_t *target) { SPIFlash.read( 0x0, target, getFilesize(object)); } }; static MyMTP MTPUSBDevice; void setup() { Serial.begin(115200); MTPUSBDevice.begin(); SPIFlash.begin(); } void loop() { delay(100); } Still working on flashing a new bitfile, dual-bitfile support and other goodies/examples. Alvie
  18. alvieboy

    Problem between AVR and FPGA

    https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/boards/papilio-duo/S6LX9/spiwb.vhd You can connect it (almost) directly to the SRAM controller https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/memory/sram/sram_ctrl8.vhd, using the pipelined-nonpipelined wrapper https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/lib/wishbone/wb_master_np_to_slave_p.vhd You don't need to worry about filtering and cross-domain clocking, the spiwb will do that for you. You can find example code in Papilio Duo documentation (wishbone access from AVR). Note that accesses are 32-bit wide and need to be aligned (and no masking is provided). Alvie
  19. alvieboy

    Problem between AVR and FPGA

    Why don't you use a SPI slave on the FPGA side ? You can reuse the one we have for wishbone access. It should work well up to 80MHz. Don't use small speeds - these are more problematic actually.
  20. alvieboy

    Use the onboard FT2232 as JTAG probe?

    I think if you hold the RESET and use the PIN header it may work... have not tried it though. I've asked Jack a couple of times for this feature (to break the chain with a jumper or similar). Don't recall his response though Alvie
  21. alvieboy

    Problem between AVR and FPGA

    You will need to eventually filter those, and also do some clock domain crosssing. All depends on exactly what you want to do. Simulation and real-world differs a lot when the IO pins are used. Care to share more information ?
  22. alvieboy

    USB controller / wing

    Felix: you got my PM ?
  23. alvieboy

    USB controller / wing

    Pics, as promised. All 5 wings now with proper headers, and packed (ESD-bag) for shipping.
  24. alvieboy

    USB controller / wing

    Ok, I just assembled and tested 5 boards (I had ordered components for 10 of them). The assembly is for USB device, but they can be reworked for USB host if needed (although we don't have any controller for it yet). These boards are transceivers, and support FS only (12Mbit/s). The bottom silkscreen is also wrong, but does not impact functiality. All boards have been hand assembled by me. I don't need all those boards, so I'll be selling them for a symbolic cost (USD$9) plus packaging+śhipping (not yet sure about how much it will be, will have to dispatch those from UK). Let me know if you want one for your experiences. I'll post some pics of the boards later today (I just realised I did not photograph them yet). Oh, yes, and PCB+śchematics too. And ZPUino code. Alvie (edit: fix "FS")
  25. alvieboy

    USB controller / wing

    Images often speak for themselves. I had to manually assign the MTP driver in Windows, but otherwise things are looking great. Alvie