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Everything posted by alvieboy

  1. How fast needs it to be ? Álvaro
  2. alvieboy

    Alpha 3

    Hi all, Alpha 3 is now out. Some stuff was not yet published as I wished (like win32 support, and some documentation), but I decided to publish anyway. Again, all news in Here are the release notes: Programmer/bootloader * Programmer now uses a dual-speed transfer. It starts at 115200 baud for identification, then ramps up speed if required. * Some bugfixes and refactoring. * Preliminary direct memory upload. Still untested. Core * New main ZPU core: ZPU Premium. You should expect almost a 3x performance increase, when compared with old core. * New PPS implementation. Things should have become clearer now. See more information on PPS page * IO selection is now clearer, so to ease adding new devices. See Implementing or porting IO devices document for more information * Fixed RAM indexing, which caused synthesis warnings Boards * Added per-board SPI clock dividers for bootloader Spartan 3E Evaluation Board * First prebuilt image for this board * Design was not being properly built, fixed that. * Changed clock speed to 96MHz, instead of 100MHz. This helps meeting timing and give accurate baud rate dividers * Fixed GPIO mappings * Added proper IO pads Documentation * Added IO device tutorial: Implementing or porting IO devices * Added Advanced IO: Advanced IO * Added PPS documentation for users: Peripheral Pin Select Known Issues * There is still no Win32 port. Some dificculties arose so I'm delaying to next release. But good news is that compiler is now built, but other parts of the toolchain still need some tweaking, as well as the IDE set up. * Resetting the serial port sometimes fails when using a real RS232 cable. This is probably due to ringing - I'll address this on next release (this only affects S3E evaluation board, but since there's a manual reset button you can get it to work) * S3E P&R is having difficulties due to both DCM used, but it does meet timing. However I'll address that on next release, to speed up the implementation process. Álvaro
  3. " Okay, now we’re beginning to feel a bit like [Alice]. This tutorial shows you how to simulate VHDL code. This code is intended to run on an FPGA and includes a software-only version of the AVR 8-bit microcontroller core. Essentially, you’ll simulate VHDL code that simulates AVR hardware. Wrap your mind around that! The code is intended to run on a Papilio Field Programmable Gate Array development board. We saw an early version of this board running the AVR8 core about a year ago. However, you don’t need to have any hardware to follow along and recreate this simulation yourself. It might be a great way to get your feet wet with FPGA programming before making that first hardware buy. Five different screencasts take you through the process of getting the AVR8 code, using an altered Arduino IDE for it, setting up a free version of Xilinx ISE to run the simulation, then setting it free and interpreting the data that the simulator spits out the other end."
  4. alvieboy

    More counters?

    I did a major rewrite to main IO module so that it is easy to connect other peripherals. I just need to test it and I'll upload to git. I will also publish ZPUIno Premium, which is a more performable core that current one. Can be up to 7 times faster, depending on operations. Álvaro
  5. alvieboy

    More counters?

    VERY VERY preliminary. Should give you a more clear view how things work: Diagrams always take some time to draw. If you have any doubt please tell me. Tomorrow I'll explain how to connect the module to IO controller, and to SPP controller (or to a physical pin). Álvaro
  6. alvieboy

    More counters?

    ZPUino includes a preliminary ADC controller, with 2Kbyte read buffer. I'm using it for an oscope project, works perfectly well at 500Ksps. I'll add a "generic" in zpuino_config.vhd to choose the timer resolution. I'll mock up a draft document today explaining how to integrate other IO cores. I'll post some news here when it's ready. Álvaro
  7. alvieboy

    More counters?

    Well, Zylin ZPU is not wishbone compliant either (the small core), but an adaptor exists that allows you to integrate some wishbone devices. Not yet But I'm planning to write one in the near term. Meanwhile if you want to do it I'll gladly help by email. Álvaro
  8. alvieboy

    More counters?

    Hi, Actually ZPUino is not (yet) wishbone compliant. Now, regarging the timers you can add as much as you want, most IO space is still free. But remember the two included timers in ZPUino are 16-bit, but they are not able to use an external trigger (however this is rather easy to implement, just tell me if you require it). In case you want to extend either the number of timers or the resolution that's also very easy to do. Álvaro
  9. alvieboy

    ZPUino Alpha 2 is out

    ZPUino Alpha 2 is out. Álvaro
  10. Do you have 2 pins you can use to temporarily connect a serial converter ? If so you can use a RS232/USB converter and I'll provide you a bitfile with ZPUino + programmer. Just upload ZPUino to FPGA and use the programmer connected to the serial converter <-> USB <-> PC to program the SPI flash. Álvaro
  11. alvieboy

    ZPUino Alpha 1 is out.

    Hi all, ZPUino Alpha 1 is out. You can find more information on the new website: Álvaro
  12. alvieboy

    CE certification/mark

    Hi, are you planning to obtain CE certification for papilio boards ? It's mandatory if you want to sell to European Union. I think it's not very hard to obtain, but I'm not a specialist on these matters. Álvaro
  13. alvieboy

    IO devices for ZPUino

    Right now, with a few HW additions, ZPUino uses 20% of an S3E500, so there should be enough room for USB host/device (if they don't require too much blockram). SRAM would be wonderful, even if we have to deploy some sort of cache to speed up things a bit.
  14. alvieboy

    IO devices for ZPUino

    Hi, ZPUino, being a SoC, includes some "classical" IO devices, such as UART, SPI and timers. It's a fairly small design however, using (as I write) only 18% of one S3E500. So there is plenty of space to implement other device handlers in hardware. One I'm already planning to add is a full USB 1.1 or 2.0 controller core (you'll only need proper transceivers). What hardware devices would you like to see on this SoC ? Right now we have: 1 UART, 2 SPI, 1 SigmaDelta, 2 16-bit timers (PWM-capable), 1 CRC16, plus 32-bit GPIO and interrupt controller. GPIO pins can have special functions, like in most SoC. That's the case for most IO pins on ZPUino. Álvaro
  15. alvieboy

    IO devices for ZPUino

    I2C should be quite straightforward to implement. Mapping registers directly should not be a good idea, because one is a 8-bit micro, the other one a 32-bit You'd lose some interesting stuff like 32-bit SPI reads. However software can be of great help here, and we can virtually map those familiar registers in the real ones. USB host (at least for USB1.1) should be very easy to implement, not quite sure about its size though. I'll take a look at Reduced MII to see what we can do about that. VGA might be harder, because we have little RAM already (are you planning any 8 or 16 bit external SRAM Wing?) Right now I'm improving bootloader and C startup routines (make them smaller and more efficient) so that we can compile C++ and use out-of-the-box. Might need some changes to toolchain code, not yet sure, but those should not be hard to do either. Álvaro
  16. alvieboy

    soft processor

    ZPUino (which is based on Zylin ZPU or ALZPU) is on the forge. Stay tuned for details (there's another Forum for it now, under Soft Processors). Álvaro