alvieboy

I have done it successfully in the past, but make sure the jumper is indeed removed. Also ensure you use as much 5V and GND wing pins as possible to lower noise and increase current capability. However, I wonder if you are replacing a PROM which used 5V as IO voltage. In this case DO NOT connect it to the wings, since IOs on the FPGA are 3.3V. There are a few solutions to convert those signals, but will depend on the IO standard (TTL or CMOS) that your system uses. If it's a TTL system, then using some 5V-tolerant buffers should do the trick. I have a design which interfaces a 3.3V FPGA to a 5V TTL system, and seems to be working OK, I can send you a link for the project if you are interested. Alvie

Try dual-PLL or dual-DCM. These are values for dual PLL on PPro (Spartan6) Input clk: 32000000.000000Hz, Output clk 95000000.000000Hz Best result: 96000000.000000Hz, error is 1000000.000000Hz PLL Mult=15, Divide=5 Scanning two-PLL approach Best result: 95000000.000000Hz, error is 0.000000Hz Master PLL: Mult=30, Divide=48 (fout=20000000.000000Hz) Slave PLL: Mult=38, Divide=8

My assumption is that the design you use only maps the first 512KB, despite having a larger SRAM. This is probably due to HDL code not properly driving the two extra address lines. Jack: can you check the synthesis/map output to see if the two uppermost address lines are actually driven by the HDL code, or just tied to '0' ? Alvie

Hi, You can store anthing you want after address 0x60000 for Papilio Pro and address 0x46000 for Papilio One. ZPUino also uses this area, so you may need to push it a bit further if you intend to use it as well. Alvaro

Try my (ZPUino) SDRAM controller. You can find here: https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/hdl/zpuino/memory/sdram It uses pipelined wishbone, so make sure you don't hold STB high after your request has been accepted. Also take a look at the PLL settings for it https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/clkgen.vhd Any issue drop me an email at alvieboy at alvie dot com Alvie

Hi Baggey, As far as I know. Xilinx EULA (End User License Agreement) forbids us from shipping the software, either in physical medium or as a download. That is the main reason you have to download it from Xilinx directly. This is far from optimal, we know, but, aside from something I believe Jack is working on (can you confirm @Jack Gassett?, the only way to get the software. Best, Alvie

Let me take a look at that and I'll get back to you. Probably there's a bug there, I don't recall testing it with non-usual modes (it's also tricy to implement). Alvie

perl -e 'use Math::Trig qw/pi/; foreach my $n(0..2047) { print int(128+100*sin($n*2*pi/2048)), "\n"; }' You should be able to translate this to other languages as well.

Ok let's look at the formula. I have not actually read that part in the manual. For the sine argument it splits the full 2*PI range into 2048 entries - so if "n" on that argument ranges from 0 to 2047, it will yield a sinewave across the full 2*PI (360 degrees). It would probably made more sense to write it as "sine( (n/2048) * (2*PI) ). Assuming you indeed want the 360 degree waveform, The waveform amplitude is given by the "100" value - since the output from sine() will be between -1 and +1, the output range [ of (sine(n*PI()/1024)+1)*100) ] will be from -100 to +100. Since you need to bias the output for 1/2 VCC (it's an 8-bit output, no negative values, hence ranges from 0 to 255, "zero" is depicted by 128) you add the 128 bias. That will make the output range from 128-100=28 to 128+100=228. You can change the amplitude at will between 0 and 127. Exactly how to create the COE file... long time I used such tools. Alvie

Just a quick note: Adding ZPUino support for AMBA/APB/AHB[-lite]/AXI is not that difficult, although we may not be 100% compliant in the first stages, due to split address+data phases on some of these protocols - still, mapping between the classic wishbone to APB and pipelined wishbone to AHB-lite should be fairly straightforward. If that eases integration with Vivado, we may as well just move to AMBA buses from the ground up. Alvie

I fixed paths (not yet on master) and generated a ZIP export file. Should work... not sure - fails on my side with: INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Care to try ? Your luck may vary... Alvie ZPUino_Papilio_One_250K_V2_blackbox_dist.zip

I need to update that project file... I do have a script able to generate the .xise file from the main Makefile/prj. However links are broken since I moved stuff around. Will do ASAP... and fix all variants in the way (I did update the main project/boards ones, not all variants though). Alvie

Yes, it's a Xilinx project. You may merge all sources into your own project if you like. However blackboxing the core (which is almost always the same) will decrease synthesis time significantly. Alvie

Can you try swapping TXD/RXD in the UCF file ? I recall we had some "misunderstanding" regarding the TX/RX direction. That was a long time ago, though. Alvie

Does your board have a "DONE" LED or pin so you can check if the FPGA starts ? Are FTDI/Serial connections the same as in original ? Why does your FPGA have a different ID code ?