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Showing content with the highest reputation since 08/06/2012 in Posts

  1. 3 points
    Hi everyone. Last year I wrote a Z80-based retro microcomputer which runs in the Papilio Pro. It started out small but I added a few interesting features, in particular a memory management unit and a 16KB cache to hide the SDRAM latency. I've ported several operating systems to it. Both the hardware and software aspects of the project have been good fun with lots of new opportunities to learn. I've just made my first public release, you can download it at http://sowerbutts.com/socz80/ and try it out. That page also describes the project in a bit more detail. RAM disk images are included to boot CP/M-2.2, MP/M-II and UZI (a UNIX system). I've included Zork and the Hitchhiker's Guide game which will play under all three operating systems; they are native CP/M application but MP/M-II implements the CP/M system calls, and UZI includes a CP/M emulator. The release also includes the full VHDL source code for the machine and the source code to all the software I've written, with the exception of the UZI port which I plan to release shortly after I extend it to support the N8VEM Mark IV SBC. Please let me know if you get it to work! This post has been promoted to an article
  2. 2 points
    Hi, I just got started with Papilio Pro last week (side note: Great work with the papilio family and wings.. Im really excited about the board's potential). The Pro was my first entry to the papilio line. I was mostly able to figure out how to get the board running and programming. But, many of the instructions/downloads on the papilio website are either outdated or directed towards Papilio One, so getting started took about 4 hours longer than I expected. I thought I'd put together a list of links and instructions for problems I encountered along the way so that perhaps others starting with the Papilio Pro could have something up-to-date (well, as of April 2013, that is): 1. Windows FTDI Drivers: I had some real trouble getting the Papilio recognized as both a USB and a virtual COM port. For my problem, the device was ALWAYS recognized on Windows-- even when I did not have the Gadget Factory drivers installed. And it never showed a virtual COM port. Troubleshooting suggests using a different cable, or editing the device properties. Apparently in my situation, the Papilio was recognized as an FTDI device first and was not using the Gadget Factory drivers. My solution: Download the FTDI CDM Uninstaller. Using FTDI's USBView utility, find the Device Vendor ID and Product ID. Use the CDM Uninstaller to uninstall the FTDI drivers for the Papilio. After plugging and replugging, Windows recognized a virtual COM port. I could also connect through putty and see the default ASCII table output which was apparently the factory default program. 2. Getting Started Bitfile: http://papilio.cc/index.php?n=Papilio.GettingStarted It appears as though the getting started website (as of April 5 2013) does not include the getting started bit file for Papilio Pro. In my beginner state, I assumed this website would have the materials I needed, so I fumbled around trying to use the Papilio One 500K bitfile. After a while, I realized it certainly doesnt make sense to try to use the Papilio One bitfile, especially since the Papilio Pro uses a completely different FPGA. I dont think I've found a replacement for the "Getting Started" bitfile for the LX9 yet. 3. Papilio Loader: As with the bitfiles, the Papilio Loader GUI on the Getting Started Page is out of date (it downloads v1.7). According to a forum discussion around December 2012, the Papilio Loader was modified to support the Papilio Pro. Download the Papilio Loader GUI specifically from the Downloads webpage (this should be version 2.1 or later): http://forum.gadgetfactory.net/index.php?/files/category/2-papilio-fpga/ 4. ZPUino Core and Loader: I think the official ZPUino download page is a little out of date for Papilio Pro. It looks like the papilio website ZPUino getting started guide is out of date too- It uses an old version of the IDE and does not include links for the Papilio Pro bitfiles. Instead a forum post indicates the RetroCade installer works with the Papilio Pro. So, to get the ZPUino to work, download the Retrocade Synth Windows Installer from the Download Page. Use the bitfile ZPUIno_SOC/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit to program the Pro. The installer should also include a version of the Arduino GUI which includes a board option for ZPUino on Papilio Pro (LX9). 5. Intro to FPGA Book: With a functioning Papilio Loader and a ZPUino core/ GUI, I was basically good to go with the Intro to FPGA E-book. I also installed the Xilinx toolchain as instructed. No issues there. I'm looking forward to generating and programming with my own bitfiles shortly. It would, however, be nice to have an updated Xilinx webpack quickstart page: http://papilio.cc/index.php?n=Papilio.XilinxISEWebpackQuickStart. EDIT: I installed the wrong Xilinx tools at first. The default link inside the Intro to FPGA E-book now leads to the Xilinx Vivado suite, which doesnt support the Spartan 3 or Spartan 6 series. Instead, make sure to download and install the ISE Design Suite. 6. Papilio Arcade: I also tried the papilio arcade wing. Just make sure to download the correct LX9 bit files from the github https://github.com/GadgetFactory/Papilio-Arcade I havent looked at the AVR8 softcore processor. This is on my list to test with the Papilio Pro, along with some other fun things (SoC editor is on the horizon too). Like I said, Im a big fan of the board. Overall, it looks to be a really great FPGA. I do want to see the usability/ learning curve get to the Arduino level, and it helps to have a good getting started procedure for all boards. Hopefully this helps another beginner in the same situation. Thanks for all the work so far! EJ
  3. 2 points
    Or any other Xilinx FPGA board with an FTDI chip with MPSSE-engine connected to the JTAG pins (like Pipistrello but not Mojo or Saturn). This is using the xilinx virtual cable driver. Playtag is written by Patrick Maupin. Steps: 1) you need python 2.7 installed. Get it here:http://www.python.org/getit/ 2) unzip the attached zip file playtag.zip somewhere on your computer 3) open a cmd-window and cd to <playtag>\tools\jtag 4) connect your Papilo board to the computer 5) type xilinx_xvc.py ftdi, this will report the available FTDI ports.You should see the A and B ports of the Papilio board (see image). 6) type xilinx_xvc.py ftdi 0, this will start the xilinx virtual cable server on the A port of the Papilo board 7) you can now use impact and chipscope etc. by selecting the xilinx_xvc plugin. Use this plugin settings: xilinx_xvc host=localhost:2542 disableversioncheck=true See attached images and zip file. Do a google-search for xilinx_xvc for more info on how to use the virtual cable driver. Magnus playtag.zip
  4. 2 points
    I had a copy of Lady Bug written by Arnim Laeuger, that I downloaded from fpgaarcade a long long time ago and forgot all about it. I recently came across it and I spent a little time getting it going for the Papilio. Unfortunately it won't fit on a Papilio One, it uses about 28 BRAMs and the Papilio One doesn't have any external memory and not enough internal memory. Good news is, it will fit entirely into a Papilio Pro or any Spartan 6 FPGA without needing any external RAM or ROM. Getting this ported to the Papilio was just a matter of writing a top level module to connect the ladybug machine to the various ROMs and input controls. This is the first time I've finally used a PS2 keyboard controller from here which appears to have a well written bidirectional PS2 controller. Bidirectional means that when you hit for example the caps lock key, the PS2 controller detects that and sends data back to the keyboard to turn on the caps lock LED. The key mapping I chose can be easily changed if you look in the source code and have a handy PS2 key code reference. As is, the game should be playable with the arrow keys. A small issue, if you have your monitor tilted one way to get other games like Pacman showing correctly, then Ladybug will appear upside down. If you can tilt the monitor the other way, you're all set, if however you can't and just reverse the state of the flip_screen_g variable, the screen will appear at first glance to be correctly flipped but unfortunately only the background is flipped, the sprites and key mapping are not, so, for example, Ladybug will appear to move the wrong way, won't line up with the corridors, eating the dots on one side of the screen causes the dots on the opposite side to disappear, etc. Currently three games are supported: Ladybug, Dorodon (a Ladybug like clone) and Cosmic Avenger (a Defender like clone). I haven't searched what other ROMs the original hardware supported, if any. The source code is available here. To make it all work, download the source then download and place the game ROMs into the appropriate ROMs folder. See the readme file in each folder for a list of the files and checksums you should be looking for, If you're on Windows, run the make_roms batch file in the relevant game rom folder. Game ROMs will be converted to vhdl files in the build directory. If you're on linux, there appears to be a makefile based system for creating ROMs and other files in the hex folder, seemed to work for me in MinGW, but I use Windows primarily. Once the ROM files are converted to VHDL, run the ladybug_papilio.xise project in the top directory and synthesize then upload to your board. You need a Papilio Pro with a Arcade Megawing and a PS2 keyboard in port "PS/2 B", VGA and audio connected. Enjoy! This post has been promoted to an article
  5. 2 points
    Well after finishing this mini project I was very sad because the Double Dragon only has a handful of (not really that great) songs it can play over the YM2151 chip. I started looking around "teh nets" for more YM2151 music and eventually I arrived in Japan so to speak. I guess since Yamaha is a Japanese company it makes sense that it was adopted as the chip of choice on local computer systems. One such very popular system is the Sharp X68000 which as the name suggests, is based on a 68000 CPU. The cool thing about this system is that it has vast amounts of music created for it, here is a hard disk image with over thirty thousand music files on it. The music is in an MML (Music Macro Language) format and typically has an extension of .MDX In fact there are two types of files, .MDX and .PDX and after a fair amount of looking into these formats it turns out that while the MDX files are the Music Macro files, the PDX files contains sampled sounds that can accompany the melodies produced via FM modulation through the MDX files. In fact the PDX files contain 4 bit ADPCM data and they could be directly feed into a chip such as the MSM5205. Another cool thing is that some very nice people have written and open sourced an MML parser that can read MDX/PDX file combos and play them via a software implementation of the YM2151 chip and some generic ADPCM decoder. It is at this point that my other post comes in. With such vast amounts of YM2151 music it was only fair to find a way to play them, so I took the source of the MML player and carved out the software YM2151 implementation (which was in fact copied from MAME's implementation of the YM2151) and only left the calls to initialize the chip and write to the registers. I then had the initialization call simply pulse the reset line to the chip while the write register calls the FTDI functions to transfer the register data to the FPGA which in turn writes it to the real chip. The result can be seen in this 4 minute video. Hope you enjoy it! If the embedded video shows in portrait mode (tall and narrow) click on the youtube logo in the bottom right corner of the video and it will show properly in landscape mode.
  6. 2 points
    Hi, I've got my SDRAM controller up and running on the Papilio Pro as well as the Logi-Pi. http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller It is running at 96MHz, but as it currently does the full "row open, read or write two words, close row" cycle for every memory access it isn't too fast. However, 24MB/s is more than fast enough if you have any audio projects in mind... flanger, delay, chorus, reverb etc Maybe somebody will write a nice roomy reverb for on the RetroCade?? 8MB is enough for 43 seconds of 48k/16bit audio. That gets you an awful lot of reverb!
  7. 2 points
    I decided to also port the Demon 3.07 verilog code to Papilio_One. This version is identical to the code running on the OpenBench Logic Sniffer board except for using 32MHz oscillator and using serial@115200 instead of SPI. It supports both meta data and input pin data query. The full XISE project can be found here: http://www.saanlima.com/download/Papilio_One/Papilio_One_OLS_3.07.zip 250K and 500K bit files are attached. Let me know if you notice any strange behavior. This post has been promoted to an articlelogic_sniffer_P1_250K.bit logic_sniffer_P1_500K.bit
  8. 2 points
    A friend of mine found a junked Hitachi LCD and gave it to me to see if I could get it going. The LCD is an older type, monochrome low resolution. I couldn't find a datasheet for it or pinouts so I went old school and tracked down datasheets for the chips on board and did some reverse engineering of the schematic using a continuity meter. A very good datasheet resource is the "Hitachi LCD Controller Driver LSI Data Book" which is a compendium of a large number of Hitachi LCD controller chips. According to the datasheet, the large chips on board are six HD61200 column shifters (IC3,4,5 and IC 6,7,8) and two HD61203 row shifters (IC 1,2). The unpopulated footprint is is a little weird with some missing pin traces (the one trace gaps on the short edge of the chip) and one less pin on one side of the chip compared to the other side. This footprint matched exactly the footprint of the HD61830 controller chip. The last unpopulated footprint of IC12 should be a SRAM chip for the IC11 controller. The LCD has one 20 pin set of connections that just go to the unpopulated IC11 controller chip. It also has a 10 pin edge connector that connects to the outputs of the IC11 controller and the inputs of the row/column shifters. It appears the PCB was designed to work in both a smart mode (with controller) and a dumb mode (no controller) hence the two different connector options. Because the controller chip was missing, I realised immediately that this LCD could not be driven in a static mode, where you just write data to the LCD internal memory and you can leave it alone to display that data. Instead this LCD would be more like a VGA display where you must constantly send data to it to refresh the picture. The 10 pin connector pinout is:1 to pin 47 IC11 D1 - pin 42 (DR) IC 3,4,5 (upper half of screen)2 to pin 10 IC11 FLM - pin 50 (DR) IC 1,23 to pin 5 IC11 MB - no connection4 to pin 11 IC11 CL1 - pin 52 (CL2) IC 1,2 and pin 37 (CL1) IC 3,4,5,6,7,85 to pin 46 IC11 CL2 - pin 40 (CL2) IC 3,4,5,6,7,86 to pin 48 IC11 D2 - pin 41 (DL) IC 6,7,8 (lower half of screen)7 to pin 29 IC11 VCC (+5V supply)8 to pin 20 IC11 GND9 to TR1 Collector (LCD bias -10V )10 to TR1 Base (LCD bias enable, contrast?) The internal chip to chip connections of the column shifters match those from the datasheet as below. Essentially each column shifter can address 80 columns and three of them are chained together to form a 240 column shifter. There is one set for addressing the top half of the screen and another set for the bottom half of the screen. The two row shifters IC1 and IC2 then select one of the 64 rows to be addressed. Together these two chips can address 128 rows but because their inputs are connected together they address the entire screen (both top and bottom of screen simultaneously) so the entire screen is refreshed in 64 cycles. In cycle 1, row 1 and row 65 are selected and a line is drawn through the top and bottom column shifters, in cycle two row 2 and row 66 is selected, etc, through to cycle 64 where row 64 and row 128 are selected. So the LCD has a resolution of 240x128 but can be throught of as two independent 240x64 areas stacked together. Input D1 sends serial pixel data to the top half of the LCD (top column shifters) and D2 to the bottom. CL2 is the LCD master clock which can go up to 2.5Mhz according to the datasheet. CL1 is the signal that latches data from the shifter outputs to the display registers, MB pin is not connected to anything and FLM is the input to the row shifters. At the start of each frame a 1 is shifted into the row shifters through FLM then zeroes are shifted for the remaining 63 cycles. This way a single bit travels through the both top 64 and bottom 64 rows selecting one row at a time in each half of the screen. Once I understood the basic function of the shifters I decided to hook it up the a Papilio One FPGA as the ideal driver hardware. Please note that the LCD panel runs off 5V whereas the FPGA outputs are 3.3V, however since the LCD does not output signals to the FPGA, it is quite safe to drive the 5V LCD inputs with 3.3V from the FPGA without using level translators. I decided to display a picture on the LCD and I picked a dithered bilevel picure of Lena. I cropped it to 256x128 resolution so it can be easily stored and displayed to the LCD without performing additional math. If I had stored the picture in its more compact 240x128 native LCD resolution I'd have to convert the LCD vertical and horizontal coordinates to ROM addresses via some math such as address = v + h*240 whereas by storing the picture as two ROMs of 256x64 bytes the v counter can directly index ROM address lines 10..5, the top bits of the h counter can index ROM address lines 4..0 and the bottom three bits of the h counter index a bit within the currently addressed ROM byte. The top half 256x64 of the 256x128 picture is stored into one 8x2K RAMB and the bottom 256x64 of the picture into another 8x2K RAMB. The reason for using two separate RAMBs is because the top and bottom of the image is shifted simultaneously so both RAMBs need to be accessed simultaneously. Another way of doing this would be to create a 16x2K memory and use 8 bits for the top and 8 bits for the bottom, or a 8x4K using 4 bits for top, 4 bits for bottom but any of these schemes would require the original image to be preprocessed and interlaced accordingly. The final code to drive the LCD ended up being very simple and is shown below. One last thing to mention is that initially I got no picture at all. After of course simulating the design to make sure the signals produced are correct and then examining the final design running on the FPGA with an oscilloscope, I saw that while the inputs to the chips had valid signals, all the outputs of the row and column drivers were sitting at 5V instead of toggling. After refering to the datasheet again I realised that these drivers need a negative Vee voltage in the range -7v to -17v. This would normally be connected to the collector of transistor TR1 and the base of TR1 could adjust the amount of voltage let through the transistor forming a contrast adjustment. Since I didn't have a handy negative supply I simply soldered a 9V battery in reverse, with the positive to the system ground and the negative directly to the Vee (emitter of TR1). This then provided the necessary negative bias to allow the LCD to display a picture. The contrast is fairly low due to the 9V battery not supplying the ideal bias voltage, I guess -12V would have been better. -- Driver for LCD type LMG6351PLYR, 240x128 resolution, monochromelibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;library unisim; use unisim.vcomponents.all;entity lcd_top isport ( RST_I : in std_logic; -- active high reset CLK_I : in std_logic; -- master clock -- D1_O : out std_logic; -- data to top half of lcd column shifter D2_O : out std_logic; -- data to bottom half of lcd column shifter CL1_O : out std_logic; -- clock CL2_O : out std_logic; -- latch display data FLM_O : out std_logic; -- row drivers input MB_O : out std_logic -- not used);end;architecture RTL of lcd_top is signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal cl1 : std_logic := '0'; signal cl2 : std_logic := '0'; signal d1 : std_logic := '0'; signal d2 : std_logic := '0'; signal flm : std_logic := '0'; signal mb : std_logic := '0'; signal bits_top : std_logic_vector( 7 downto 0) := (others=>'0'); signal bits_bot : std_logic_vector( 7 downto 0) := (others=>'0'); signal mainctr : std_logic_vector( 3 downto 0) := (others=>'0'); signal hctr : std_logic_vector( 7 downto 0) := (others=>'0'); signal vctr : std_logic_vector( 5 downto 0) := (others=>'0');begin -- input assignments rst <= RST_I; clk <= CLK_I; -- output assignments FLM_O <= flm; CL1_O <= cl1 and (not cl2); CL2_O <= cl2; D1_O <= d1; D2_O <= d2; MB_O <= mb; -- divide main 32Mhz clock by 16 to get 2Mhz clock clk_inst : process(clk) begin if rising_edge(clk) then mainctr <= mainctr + 1; end if; end process; -- 2Mhz clock (max 2.5Mhz per datasheet) cl2 <= mainctr(3); -- horizontal counter hctr_inst : process(cl2, rst) begin if (rst = '1') then hctr <= (others=>'0'); elsif rising_edge(cl2) then if hctr = 239 then hctr <= (others=>'0'); else hctr <= hctr + 1; end if; end if; end process; -- vertical counter vctr_inst : process(cl2, rst) begin if (rst = '1') then vctr <= (others=>'0'); elsif rising_edge(cl2) then if vctr = 64 then vctr <= (others=>'0'); elsif hctr = 239 then vctr <= vctr + 1; else vctr <= vctr; end if; end if; end process; -- generate CL1 (display data latch) cl1_inst : process(cl2) begin if falling_edge(cl2) then if (hctr = 239) then cl1 <= '1'; else cl1 <= '0'; end if; end if; end process; -- generate FLM flm_inst : process(cl2) begin if falling_edge(cl2) then if (hctr = 239) and (vctr = 0) then flm <= '1'; else flm <= '0'; end if; end if; end process; -- image data shifters bit_inst : process(cl2) begin if rising_edge(cl2) then case hctr(2 downto 0) is when "000" => d1 <= bits_top(7); d2 <= bits_bot(7); when "001" => d1 <= bits_top(6); d2 <= bits_bot(6); when "010" => d1 <= bits_top(5); d2 <= bits_bot(5); when "011" => d1 <= bits_top(4); d2 <= bits_bot(4); when "100" => d1 <= bits_top(3); d2 <= bits_bot(3); when "101" => d1 <= bits_top(2); d2 <= bits_bot(2); when "110" => d1 <= bits_top(1); d2 <= bits_bot(1); when "111" => d1 <= bits_top(0); d2 <= bits_bot(0); when others => null; end case; end if; end process; -- top and bottom of screen image ROMs ROM_TOP : entity work.ROM_TOP port map ( CLK => clk, ENA => '1', ADDR (10 downto 5) => vctr, ADDR ( 4 downto 0) => hctr(7 downto 3), DATA => bits_top ); ROM_BOT : entity work.ROM_BOT port map ( CLK => clk, ENA => '1', ADDR (10 downto 5) => vctr, ADDR ( 4 downto 0) => hctr(7 downto 3), DATA => bits_bot );end RTL;
  9. 2 points
    I've just finished my 8 digit frequency counter - I'm just waiting for a GPS module to arrive so I can use it as the reference timesource. Here's a block diagram of the project: And here is a photo of it in action, when using a one pulse per second generated from the local Xtal as the reference. Full source is up on my wiki at http://hamsterworks....equency_counter This post has been promoted to an article
  10. 2 points
    3 bit of green, 3 bit of red, and 2 bit of blue. http://en.wikipedia.org/wiki/8-bit_color
  11. 1 point
    One mini one micro at least avoids getting them the wrong way around
  12. 1 point
    papilio-prog is not the same as xc3sprog. papilio-prog was forked off from xc3sprog way back and is using a different bscan file. I have attached a zip file with the vhdl source file as well as the ucf file for the qfp144 package. Hope this helps, Magnus bscan.zip
  13. 1 point
    I've ordered a batch of PCB from Seeed (ETA 3 weeks). If anybody would like one (less the through-hole components) just drop us a line. The pins are laid out for the Adafruit Themocouple Amp/ADC board, but should work with andything. It also has four general purpose LEDs on it
  14. 1 point
    FYI, there is now a 32-bit 5V-tolerant buffer wing available for Papilio and Pipistrello boards. The 32-bit I/O bus is divided into four groups of 8 with individual direction and enable control for each group. The wing is designed for use with the Open Bench Logic Sniffer code. See http://saanlima.com/store/index.php?route=product/product&product_id=55 for more info and schematic.
  15. 1 point
    Hi folks, I'd like to show off my first Papilio Pro project. It's not much by anybody else's standards, but I was quite excited to get to this point after only a couple of days, starting from zero knowledge. Mike Field's tutorial was awesome! I hope that this is an appropriate use of this forum. I realize that others on the forum seem to be much more sophisticated. The project continuously increments a 16-bit counter, then renders that counter on the LED display. The project has three components: one that does the counter, one that multiplexes the counter onto the display, and one that translates 4-bit hex nibbles into 7-segment values suitable for display. I'm actually quite surprised that it worked without too much pain. I had to guess here and there. Here's a video: http://www.flickr.com/photos/15819666@N00/10388671913/ My .vhd and .ucf files are attached. I called the top-level file "Beef" because it was displaying 0xBEEF in the earlier stages of the design. I also had a couple of questions if you don't mind. 1 - I notice that the software spews out a huge number of files into my working directory. Is there a way to cleanly separate my source files from all these tool-generated intermediate files? An analogy in the C++ world is that I'd like to keep my .cc, .h, and Makefiles in a separate place from the .o and executable files. This makes for easy management with version control and also easy sharing (there's no point in checking in or sharing all these tool-generated intermediate files). What do other people do here? 2 - In a case statement (such as that in SevenSegMultiplexor.vhd) I tend to need a line like ``when others => ENABLES <= "XXXX";'' I was staring at the 9-valued logic page in Wikipedia and I couldn't decide whether I wanted "XXXX", "WWWW", "UUUU", or "----" here. I actually would have guessed "----" meaning `don't care` but XXXX seemed to work without complaint. Which is the most appropriate? 3 - I could have inlined HexTo7Seg inside SevenSegMultiplexor but I liked the way it looked as a separate component. Is this a reasonable thing to do? Any advice would be greatly appreciated. And thanks! I've had a fun weekend! This post has been promoted to an articlecounter project.zip
  16. 1 point
    Mike, set the PLL's CLKFBOUT_MULT parameter to 25 and the various CLKOUT<n>_DIVIDE parameter to 8 and you get 100 MHz. 32 MHz * 25 yields an FB clock of 800 MHz. Pages 56/57 of the spartan 6 data sheet (ds162) give the min/max PLL operating range. Fvcomin is 400 MHz, and Fvcomax is 1000 MHz. If you feed the PLL 32 MHz and specify MULT=3, DIVIDE=1, you will be out of spec. BTW, the download link for your papilio pro zip file is messed up -- clicking on it leads to the message saying I don't have permission to upload that file!
  17. 1 point
    So I've just finished my latest project - an FPGA based FM transmitter that beeps out SOS in Morse code. All you need is a wire and 60 lines of VHDL! http://hamsterworks....ndex.php/FM_SOS I was musing over it all day and decided to give it a try. There I was feeling extra clever at how well it works, and upload the a video of it in operation to Youtube. As soon as it finished it recommends that I might want to watch another video - it is somebody transmitting music on FM using only an FPGA. I don't feel so clever now! This post has been promoted to an article
  18. 1 point
    Short answer - no. It takes about 11 cycles to read or write a byte from SDRAM, and maybe another 8 if a refresh cycle is needed. So if you are using 100MHz SDRAM you could only make it look like SDRAM if you ran your project at under 5MHz. To make good use of SDRAM your design must decouple most of your access to memory - either by caching, busting data into FIFOs, careful scheduling or some other magic...
  19. 1 point
    hamster: indeed this does not meet timing for 720p (74.25MHz pix clock). Some issues are in my FIFO (although it does not care about timings - it will work with even almost-zero setup), but the serializer is not happy.... Slack (setup path): -0.280ns (requirement - (data path - clock path skew + uncertainty)) Source: hdmi_inst/mydvid/latched_green_3 (FF) Destination: hdmi_inst/mydvid/shift_green_3 (FF) Requirement: 2.693ns Data Path Delay: 1.800ns (Levels of Logic = 1) Clock Path Skew: -0.670ns (1.513 - 2.183) Source Clock: hdmi_clk_pix rising at 0.000ns Destination Clock: hdmi_clk_p rising at 2.693ns Clock Uncertainty: 0.503ns Clock Uncertainty: 0.503ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.558ns Phase Error (PE): 0.222ns Maximum Data Path at Slow Process Corner: hdmi_inst/mydvid/latched_green_3 to hdmi_inst/mydvid/shift_green_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X20Y60.CQ Tcko 0.525 hdmi_inst/mydvid/latched_green<4> hdmi_inst/mydvid/latched_green_3 SLICE_X18Y58.B4 net (fanout=1) 0.926 hdmi_inst/mydvid/latched_green<3> SLICE_X18Y58.CLK Tas 0.349 hdmi_inst/mydvid/shift_red_4_BRB1 hdmi_inst/mydvid/Mmux_GND_243_o_latched_green[9]_mux_6_OUT41 hdmi_inst/mydvid/shift_green_3 ------------------------------------------------- --------------------------- Total 1.800ns (0.874ns logic, 0.926ns route) (48.6% logic, 51.4% route) Clock skew looks very high. Same for jitter. I wonder if this can be improved... Note: I haven't tried to plug the HDMI from this one yet... might work, might not...
  20. 1 point
    I hope this doesn't breach any forum rules and I have no vested interest in the sales of this product but I remember a while back there quite a few people raving/drooling over Zynq boards but not able to afford them. It turns out now that Adapteva has met their funding campaign and will start shipping Zynq boards to fund contributors but will also accept pre-orders for the same $99 price for Zynq7010 boards, upgradeable to Zynq7020 (unknown price). For those not in the know, the Zynq7010/7020 combine a dual core A9 1GHz ARM CPU with Artix-7 level FPGA in a single package allowing one to combine the software programmability of the ARM core with hardware programmability of the FPGA core, letting you bolt on any custom hardware you care to design to the existing ARM cores.
  21. 1 point
    Ok, here's the first prototypes: I've got a set like this going out to Jack and Alvie for testing.
  22. 1 point
    Which FPGA was used for this batch?
  23. 1 point
    There really isn't a lot to the hardware side of things, I don't think. Check out this example: http://www.arduino.cc/en/Tutorial/Potentiometer. All that's done is hook up the pot to +5, G and then to a GPIO. The tough part is going to be updating the software to do what you want. The easy way to do it without building anything is to use the onboard MIDI capability and get a control surface like the Kork nanoKONTROL or Behringer BCR and then map those controls to the functions you want to control. There is also a new MIDI library for Android that looks pretty promising. I have yet to try it out, but if you have USB OTG capability on your phone,it would be possible to create a control surface on the phone. I am actually really interested in doing this for the Retrocade
  24. 1 point
    Wow, I haven't noticed the sudden activity on this thread. I agree with Jack, the economy to market a board like Pipistrello is not very good. The component cost alone (parts and the PCB) for the LX45-3 version is about $100/board for a batch of 50 boards. The assembly of a board like this at volumes like this is about $35/board, then comes testing and possibly rework etc for defect boards. To make any money the board needs to sell for close to $200 but I don't think the hobbyist market will support that. I have been selling pre-production boards for $140 just because I want to make a board like this available but it's obvious that this is a hobby of mine and not a money maker at this point, so I don't think Jack needs to be worried It would be different if Xilinx supported makers of boards like Papilio and Pipistrello but no luck so far. Hey Alex, you didn't mind when I posted code updates from Pipistrello to fix the Papilio Loader for Papilio Pro
  25. 1 point
    I think it has been summed up fairly well here. The schematic entry is a great route for beginners and makes it dead easy to get something up and running. For a very visual person like myself, I found it to be an invaluable way to break the ice and familiarize myself with the tools and concepts. It is possible to implement fairly complex designs via schematic entry, but as has been said, it starts to get very tedious. What I've been doing is transitioning more and more towards VHDL, using a mix of the two methods. One of the really cool things about all this is that it's possible to almost seemlessly mix and match HDLs within the same project, since unlike a programming language, your code is describing the way hardware is wired up rather than executing instructions. Schematic is great for simple stuff like you would put into a small to midsized CPLD, but once you get to something that really utilizes a FPGA, you will quickly find that it gets unbearably tedious and unweildy. A pencil & paper to sketch and visualize the logic as you write the HDL code can be a lot less tedious than the schematic editor.