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Showing content with the highest reputation on 03/02/2016 in all areas

  1. 1 point
    I don't have a Nexsys 3 board but from the schematic the clock coming in on Pin V10 is a 100MHz clock. You can't define it differently in the ucf, even if you do it will still be 100MHz. You need to run it into a DCM and generate the appropriate clock, which looks like it needs to be 20MHz. Use the IP manager in ISE or Vivado to do that, then instantiate it where it tells you to in the top level file (below line 52 in the original, it says -- use a DCM to generate 20Mhz clock required by VGA process)
  2. 1 point
    I finally got to a computer and was able to download your original file and can see some of your problems. 1) You declare the VGA signals correctly in the top level entity on lines 15-17 as std_logic_vector but on lines 26-28 you need to keep VideoR, VideoG and VideoB as std_logic, not std_logic_vectors. This will fix the errors that come up on lines 88, 90 and 93 during synthesis. Change lines 26-28 to this: signal VideoR : std_logic; signal VideoG : std_logic; signal VideoB : std_logic; 2) On line 46 do connect the signal VideoR to each bit of the O_VIDEO_R like this: O_VIDEO_R <= VideoR & VideoR & VideoR; Do the same for the other two colors: O_VIDEO_G <= VideoG & VideoG & VideoG; O_VIDEO_B <= VideoB & VideoB; -- only 2 bits. That should get you through synthesis. Now for the Place & Route, you need to make sure you have the correct signal names in the ucf file. You need to uncomment (remove the leading #) and match the names to the names on your top level entity. For example on the nexys3_master.ucf you need the change line 156 to: NET O_VIDEO_R<0> LOC = "U7" | IOSTANDARD = "LVCMOS33"; do this for all the signals on your top level entity. I think that will get you through all the problems I can see.
  3. 1 point
    His errors seem to come from a different part of the HDL, hence me asking for him to post the whole source. Note the source lines in the error messages.
  4. 1 point
    I went to google code and looked at the original source your are trying to modify. I don't know what other mods you made but from what I can see the errors you are getting above are caused by the fact that you didn't change the O_VIDEO_x signals into vectors. You are also trying to connect the outputs to the internal signal in some cases, it only works the other way around. Since the top level signals you are trying to make into 2 or 3 bit vectors are defined as std_logic right now if you want to make them 3 bit std_logic_vectors you need to do this: change O_VIDEO_R : out std_logic; to O_VIDEO_R : out std_logic_vector(2 downto 0); in the entity definition (line 15 in the original code). Do the same for the O_VIDEO_G and O_VIDEO_B, if you want them to be 2 bit instead of 3 then define them as std_logic_vector(1 downto 0); then where the O_VIDEO_R is connected to the internal signal in the architecture (line 46 in the original code) connect it like this: O_VIDEO_R <= VideoR & VideoR & VideoR; Do the same thing for G and B. The other thing you have to do is make changes in the constraints file to account for these extra bits. The ucf files have the bits defined already you just need to comment out the original O_VIDEO_R (and G and B ) lines by inserting a pound sign in front of them (#) then remove the pound sign from the front of the lines that you want to connect, like O_VIDEO_R(2), O_VIDEO_R(1), O_VIDEO_R(0) and make sure all the signals are connected to the right pins on the FPGA.