Leaderboard


Popular Content

Showing content with the highest reputation on 02/27/2016 in all areas

  1. 1 point
    I agree with Jaxartes that when going from one bit to multibit vectors connection of the single bit to all bits of the vector is a better solution, go from zero to full scale. Thanks for correcting that. If you want to go the other way from multibit to one bit you would use just the msbit of the vector as its transition from 0 to 1 represents the mid point. This is only on unsigned of course.
  2. 1 point
    When it comes to VGA output, different boards will have different numbers of digital pins used to generate the analog color lines. On Papilio the VGA Wing uses three (one per color component), the LogicStart MegaWing uses eight (2-3 per color component), and the Arcade MegaWing uses twelve (4 per color component). So when adapting a design, meant for one of them, to another, you have to change the relevant parts. As for the errors you're getting, I can't be much help, as I don't work usually with VHDL but with Verilog instead. But what I suspect is that there's a difference between a single logic signal (STD_LOGIC) and an array of some number of logic signals (STD_LOGIC_VECTOR) even if the "some number" is 1. I believe that's the same thing treadstone says above. You might have to make small changes to the syntax of the VHDL code to change one to the other. To up convert from one bit per component to three or four, you can do what treadstone suggests above (make that one bit the msb, and fill the rest in with zero) though what I'd usually do instead is copy that one bit to all three or four.
  3. 1 point
    Yeah, I can see that. I don't know exactly what's causing the error but my guess is: That 'video_ram' was meant for the Spartan-3 FPGA found in the Papilio One board, and not the Spartan-6 FPGA you're building it for. A lot of Verilog or VHDL code is portable, but some things which use vendor primitives might not be. And it looks like video_ram is one of those; see "https://github.com/thelonious/vga_generator/blob/master/vga_text/ipcore_dir/video_ram.v". I see two options for fixing it: (a) Use Xilinx's core generator to make one that will be suitable for Spartan-6; or ( write one which can be inferred and therefore will be more portable. I would usually choose ( but I'm afraid neither (a) nor ( is really easy. (a) is explained in chapter 15 of the eBook linked here: http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/intro-to-spartan-fpga-ebook-r34
  4. 1 point
    I don't have the code you referenced but I am assuming it is displaying a seven segment on vga. Maybe you are trying to connect the virtual seven segment lines to the vga lines. I believe the errors you are getting are because you are attempting to connect a std_logic_vector to a std_logic signal. If you are trying to connect a one bit vga signal to a three bit you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.
  5. 1 point
    Regarding the error message: I can't read it in your post, it just shows up as "?" for some reason. Regarding how to "call" it: The "Code x32" means "character code 0x32". That is, when the value 50 (0x32) is found in the video_ram, the corresponding font data (what you quoted above) is displayed on the screen. So the question for you is how to get the codes for "hello world" into the video_ram. It looks like emitCharCodes.pl is part of that process. I think it's used to generate a new video_ram.coe file, and then you build the whole thing using ISE.