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  1. 2 points
    Original version of game was running on PIC18F6622 and Dingoo A320. Now it's running on Papilio One 500K + Arcade Megawing. I've used the ZPUino soft processor which is realized by Xilinx Spartan-3E FPGA. VGA signal is also generated by the FPGA. The game can be played with integrated buttons of Arcade Megawing or with Atari/Commodore joysticks. I've used a QuickShot II Plus (SVI-102 Plus) joystick in the video below: Demo Please, use the .bit file included in the ZIP. Otherwise buttons and joystick are not working properly. sometris_v121.zip
  2. 2 points
    I have the J1 CPU running on the Papilio Duo. It runs a standard 32-bit ANS Forth, communication is through the UART. It is working quite well; in fact I used it to run my slides for a presentation last week (slides were on microSD, buttons and VGA output from the Computing Shield). Is anyone interested in giving it a tryout? Let me know if so and I will put together a release. Thanks! J.
  3. 1 point
    Hi, I just got started with Papilio Pro last week (side note: Great work with the papilio family and wings.. Im really excited about the board's potential). The Pro was my first entry to the papilio line. I was mostly able to figure out how to get the board running and programming. But, many of the instructions/downloads on the papilio website are either outdated or directed towards Papilio One, so getting started took about 4 hours longer than I expected. I thought I'd put together a list of links and instructions for problems I encountered along the way so that perhaps others starting with the Papilio Pro could have something up-to-date (well, as of April 2013, that is): 1. Windows FTDI Drivers: I had some real trouble getting the Papilio recognized as both a USB and a virtual COM port. For my problem, the device was ALWAYS recognized on Windows-- even when I did not have the Gadget Factory drivers installed. And it never showed a virtual COM port. Troubleshooting suggests using a different cable, or editing the device properties. Apparently in my situation, the Papilio was recognized as an FTDI device first and was not using the Gadget Factory drivers. My solution: Download the FTDI CDM Uninstaller. Using FTDI's USBView utility, find the Device Vendor ID and Product ID. Use the CDM Uninstaller to uninstall the FTDI drivers for the Papilio. After plugging and replugging, Windows recognized a virtual COM port. I could also connect through putty and see the default ASCII table output which was apparently the factory default program. 2. Getting Started Bitfile: http://papilio.cc/index.php?n=Papilio.GettingStarted It appears as though the getting started website (as of April 5 2013) does not include the getting started bit file for Papilio Pro. In my beginner state, I assumed this website would have the materials I needed, so I fumbled around trying to use the Papilio One 500K bitfile. After a while, I realized it certainly doesnt make sense to try to use the Papilio One bitfile, especially since the Papilio Pro uses a completely different FPGA. I dont think I've found a replacement for the "Getting Started" bitfile for the LX9 yet. 3. Papilio Loader: As with the bitfiles, the Papilio Loader GUI on the Getting Started Page is out of date (it downloads v1.7). According to a forum discussion around December 2012, the Papilio Loader was modified to support the Papilio Pro. Download the Papilio Loader GUI specifically from the Downloads webpage (this should be version 2.1 or later): http://forum.gadgetfactory.net/index.php?/files/category/2-papilio-fpga/ 4. ZPUino Core and Loader: I think the official ZPUino download page is a little out of date for Papilio Pro. It looks like the papilio website ZPUino getting started guide is out of date too- It uses an old version of the IDE and does not include links for the Papilio Pro bitfiles. Instead a forum post indicates the RetroCade installer works with the Papilio Pro. So, to get the ZPUino to work, download the Retrocade Synth Windows Installer from the Download Page. Use the bitfile ZPUIno_SOC/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit to program the Pro. The installer should also include a version of the Arduino GUI which includes a board option for ZPUino on Papilio Pro (LX9). 5. Intro to FPGA Book: With a functioning Papilio Loader and a ZPUino core/ GUI, I was basically good to go with the Intro to FPGA E-book. I also installed the Xilinx toolchain as instructed. No issues there. I'm looking forward to generating and programming with my own bitfiles shortly. It would, however, be nice to have an updated Xilinx webpack quickstart page: http://papilio.cc/index.php?n=Papilio.XilinxISEWebpackQuickStart. EDIT: I installed the wrong Xilinx tools at first. The default link inside the Intro to FPGA E-book now leads to the Xilinx Vivado suite, which doesnt support the Spartan 3 or Spartan 6 series. Instead, make sure to download and install the ISE Design Suite. 6. Papilio Arcade: I also tried the papilio arcade wing. Just make sure to download the correct LX9 bit files from the github https://github.com/GadgetFactory/Papilio-Arcade I havent looked at the AVR8 softcore processor. This is on my list to test with the Papilio Pro, along with some other fun things (SoC editor is on the horizon too). Like I said, Im a big fan of the board. Overall, it looks to be a really great FPGA. I do want to see the usability/ learning curve get to the Arduino level, and it helps to have a good getting started procedure for all boards. Hopefully this helps another beginner in the same situation. Thanks for all the work so far! EJ
  4. 1 point
    This is a library for Designlab and Papilio Duo. The decoder module can have up to 4 encoders. For example 4 wheels on a mobile robot platform. Optionally this can be use with a PID regulator for controlling current position, velocity, and direction of an object. - The shown pins are totally optional - By default the Avr chip is disabled Download: Quadrature_decoder.zip
  5. 1 point
    Hi all, I know it will sound stupid, but anyone knows if I have to enable something in ISE (14.7) to get the symbol manager? I followed the tutorial on the learning site but, after I loaded the example project, the Tools dropdown ends with "Smart Xplorer" and there are no other options as on the screenshot..... Where am I missing the point? :-D Thanks!
  6. 1 point
    When it comes to VGA output, different boards will have different numbers of digital pins used to generate the analog color lines. On Papilio the VGA Wing uses three (one per color component), the LogicStart MegaWing uses eight (2-3 per color component), and the Arcade MegaWing uses twelve (4 per color component). So when adapting a design, meant for one of them, to another, you have to change the relevant parts. As for the errors you're getting, I can't be much help, as I don't work usually with VHDL but with Verilog instead. But what I suspect is that there's a difference between a single logic signal (STD_LOGIC) and an array of some number of logic signals (STD_LOGIC_VECTOR) even if the "some number" is 1. I believe that's the same thing treadstone says above. You might have to make small changes to the syntax of the VHDL code to change one to the other. To up convert from one bit per component to three or four, you can do what treadstone suggests above (make that one bit the msb, and fill the rest in with zero) though what I'd usually do instead is copy that one bit to all three or four.
  7. 1 point
    I don't have the code you referenced but I am assuming it is displaying a seven segment on vga. Maybe you are trying to connect the virtual seven segment lines to the vga lines. I believe the errors you are getting are because you are attempting to connect a std_logic_vector to a std_logic signal. If you are trying to connect a one bit vga signal to a three bit you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.
  8. 1 point
    Regarding the error message: I can't read it in your post, it just shows up as "?" for some reason. Regarding how to "call" it: The "Code x32" means "character code 0x32". That is, when the value 50 (0x32) is found in the video_ram, the corresponding font data (what you quoted above) is displayed on the screen. So the question for you is how to get the codes for "hello world" into the video_ram. It looks like emitCharCodes.pl is part of that process. I think it's used to generate a new video_ram.coe file, and then you build the whole thing using ISE.
  9. 1 point
    And we were able to do a full simulation of the system, so we can find bugs on it.
  10. 1 point
    Hi Alvie, I'm building at the moment directly the s3e500 under papilio-one from your github without changes and I also run it on a Papilio-one with S3e500. So its correct that it's not LX9. After I get everything running on the one I want to move to the LX9. Tobias
  11. 1 point
    For more info see: https://www.llnl.gov/news/nih-taps-lab-develop-sophisticated-electrode-array-system-monitor-brain-activity The NIH project is a collaboration between LLNL's Neural Technology Group; the laboratory of Loren Frank at University of California, San Francisco (UCSF); Intan Technology; and SpikeGadgets. Housed at the Center for Bioengineering, the Neural Technology Group will work with UCSF researchers to design and build electrode arrays that can record hundreds to thousands of brain cells simultaneously. Their goal is to develop 1,000-plus channel arrays that can eventually be expanded to 10,000 channels. These arrays will use new microchips designed at Intan and will send data to a system developed at SpikeGadgets. UCSF will coordinate these efforts and test the technologies. The arrays will penetrate multiple regions of the brain without interfering with normal functions during the experiments, allowing for detailed studies of brain circuits that underlie behavior. "This collaboration combines the engineering talent of LLNL with UCSF's expertise in neural recording and modulation systems, and the design and programming skills of Intan and SpikeGadgets," Frank said. "The result will be a system that will help us understand how different brain areas communicate and carry out complex mental functions."
  12. 1 point
    And I happen to work on a system that samples up to 1024 analog signals each 16-bit at 30 kHz sampling rate using up to 16 ADCs, each with a 64 ch mux All done with an Spartan6 LX16 and streaming the data out using a TMDS link (i.e. like HDMI but just clock and data) at 78.6 MB/s. using regular HDMI connectors and cables. For something like this you definitely need an FPGA. Here is a picture of a 640 ch system. FPGA board to the right with micro-HDMI connector for power and data, 5 ADC boards in the middle, each with 2 ADCs (i.e. 128 ch each), and LVDS terminator board to the left. The ADCs are connected to the FPGA using SPI with LVDS signaling (CS, CLK, MOSI, 16x MISO).
  13. 1 point
    glad it worked out. have a great weekend also
  14. 1 point
    Hi Im new to FPGA but have one question: Concerning Commodore MOS chips Is there open source for: 1351 Mouse Controller C64/C128 Ram chips REC memory controller SID: 6581,6582,8580 last known revisions? The last item is: I have heard that CBM MOS chips could possibly be redone using xilinx using PLD but its difficult but would any of the Papilio code still work with Xilinx software? Is there any open source for anything like the CBM MOS 1351 controller chip. (1351 was CBM Mouse, worked in Joystick Mode and Proportional mode). Other controllers wont work because the 1351 somehow worked along with the SID Oscillator, without that it wouldn't work. I hope I asked this in the right forum so any help is appreciated. Thank you, Terry Raymond
  15. 1 point
    it works. Using this Source and the Device source: http://www.macronix.com/Lists/ApplicationNote/Attachments/1148/AN0245V2%20-%20Using%20Macronix%20Serial%20Flash%20with%20Xilinx%20iMPACT%20Tools.pdf part: N25Q64
  16. 1 point
    @Jack - maybe we need to make testbed files for the p500 like i did for the pduo ? @island_peter - if you want to send your p500/arcade megawing to me i can test it for you ( i live near wiesbaden ) but as jack said, RomVault - Papilio Edition is a good way to test since it comes with a few free games and it loads them with just 2 clicks.
  17. 1 point
    Thank you very much for this project. I've been wanting to try and receive some kind of low-res digital video signal, say 640x480, for a while. For some (misguided) reason I started by reading the DisplayPort standard, but I quickly realized it's waaay too complex for my abilities. Compared to it, HDMI / DVI-D seems a piece of cake. I mean, It even comes with its own clock line! Actually I never knew HDMI was just DVI-D repackaged. That's quite sleazy of them. I don't have a Papilion (yet). Would you strongly recommend using an FPGA with builtin support for TMDS? Said another way, what kind of circuit would I need to hook the TMDS pairs to a simple CPLD, or maybe to a Cyclone IV? (which is what I have atm.*) I don't have any experience with differential transmission lines, so if it's more complicated than a few components, I'll just get a Papilion. Finally, I couldn't find the schematics for your wing board on your wiki, could you please send me a copy? Even if it's just a sketch or a screenshot, I'm a beginner and every bit helps * Cyclone IV datasheet says "Differential I/O: SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS" but I don't have a clue whether any of them are physically compatible with TMDS!
  18. 1 point
    I'm only using the FPGA on my Papilio DUO, so I force the AVR into reset by setting ARD_RESET (FPGA pin 139) low. I think this makes all AVR I/Os high-impedance.
  19. 1 point
    Heh, "pay $10 more OR we will solder the connectors to the wrong side" Anyway, Zynq could be an interesting chip for the future. On a "fun" scale, Xilinx ISE is about the same as DIY dental surgery. Maybe Vivado improves on that...
  20. 1 point
    Its true all logic compilers are bad at producing relevant error messages and can lead users on a wild goose chase, the most common message being 'its broken and I am not telling you why'
  21. 1 point
    IMO the biggest challenge facing FPGA development boards is cost. A Raspberry Pi 2 or ODROID-C1 is US$35 for a desktop-capable quad-core ARMv7 with 1 GB RAM, quad (or more) USB 2.0, and Ethernet. The cheapest Spartan-6 board I have seen from a reputable vendor is about US$70, twice as much. I had hopes for the Hackaday Arduino-Compatible FPGA board when it was first announced at US$50, but now it's up to US$70. US$35 is a great price point, because it's at a level that a hobbyist can buy without spousal approval and something students can afford. US$25 would be even better for an FPGA board. If you look at Spartan-6 LX9 pricing, it's not the chip cost. The problem is that FPGA boards aren't popular enough to manufacture in 10K or larger lots, like Raspberry Pi. The fact that there are so many different FPGA boards diluting an already small market makes the problem worse. So I would recommend designing an FPGA board that really drives the price down. I really like the Butterfly Platform that Jack posted upstream. Very simple board, with just an FPGA, bypass caps, and connectors. Spartan-6 is nice because you only need 3.3V and 1.2V -- you don't need 2.5V like the Spartan-3E. While I like having an FT2232H on board for programming, the fact is that those chips are pricey. For US$15 you can get an Adafruit FT232H breakout board which makes a dandy JTAG programmer, and you can use it for all your FPGA boards. The other big challenge is the steep learning curve of vendor FPGA software, but a number of us are working on that with various approaches. If it the software was a lot easier and there was a really cheap board we could help a lot of new FPGA users get started. JMO/YMMV
  22. 1 point
    Hi guys, I just wrote a small C++ application (text-mode) that can compute the two primary configuration values for PLL (multiply and divide), given an input clock speed and the required speed. Since some of these are not possible directly using a single PLL, the application also scans for a dual-chained PLL approach, where the output from the first PLL is fed into the input of the second PLL. These two parameters are enough for you to get a working PLL with your desired frequency. Source code and prebuilt windows .exe available at: http://alvie.com/zpuino/downloads/pllscan/ Enjoy Alvie
  23. 1 point
    I decided to also port the Demon 3.07 verilog code to Papilio_One. This version is identical to the code running on the OpenBench Logic Sniffer board except for using 32MHz oscillator and using serial@115200 instead of SPI. It supports both meta data and input pin data query. The full XISE project can be found here: http://www.saanlima.com/download/Papilio_One/Papilio_One_OLS_3.07.zip 250K and 500K bit files are attached. Let me know if you notice any strange behavior. View attachment: logic_sniffer_P1_250K.bit View attachment: logic_sniffer_P1_500K.bit
  24. 1 point
    Assuming the need to go to multi-layer for the BGA part, that looks like it will be a very expensive board. You might look at a part such as the XC3S500E-4PQG208I which is in a 208 pin PQFP package. The FPGA is a bit more expensive but the PCB will be a fraction the cost if you can keep it to 2 layers. Also at least when it comes to Seeed, the cost of the board increases rapidly with size. 5cm * 5cm max is around $1/bd, 10cm * 10cm max is $2.50/bd, while the next size up, 15cm * 15cm max is close to $9/bd. If you can manage to keep it within 10cm square then the bare boards are ridiculously cheap.
  25. 1 point
    Latest code for windows and linux32 can be found here: http://pipistrello.saanlima.com/index.php?title=Arduino-1.5.2_on_Pipistrello