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Showing content with the highest reputation since 05/22/2015 in all areas

  1. 2 points
    Original version of game was running on PIC18F6622 and Dingoo A320. Now it's running on Papilio One 500K + Arcade Megawing. I've used the ZPUino soft processor which is realized by Xilinx Spartan-3E FPGA. VGA signal is also generated by the FPGA. The game can be played with integrated buttons of Arcade Megawing or with Atari/Commodore joysticks. I've used a QuickShot II Plus (SVI-102 Plus) joystick in the video below: Demo Please, use the .bit file included in the ZIP. Otherwise buttons and joystick are not working properly. sometris_v121.zip
  2. 2 points
    I have the J1 CPU running on the Papilio Duo. It runs a standard 32-bit ANS Forth, communication is through the UART. It is working quite well; in fact I used it to run my slides for a presentation last week (slides were on microSD, buttons and VGA output from the Computing Shield). Is anyone interested in giving it a tryout? Let me know if so and I will put together a release. Thanks! J.
  3. 1 point
    I don't have the code you referenced but I am assuming it is displaying a seven segment on vga. Maybe you are trying to connect the virtual seven segment lines to the vga lines. I believe the errors you are getting are because you are attempting to connect a std_logic_vector to a std_logic signal. If you are trying to connect a one bit vga signal to a three bit you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.
  4. 1 point
    Regarding the error message: I can't read it in your post, it just shows up as "?" for some reason. Regarding how to "call" it: The "Code x32" means "character code 0x32". That is, when the value 50 (0x32) is found in the video_ram, the corresponding font data (what you quoted above) is displayed on the screen. So the question for you is how to get the codes for "hello world" into the video_ram. It looks like emitCharCodes.pl is part of that process. I think it's used to generate a new video_ram.coe file, and then you build the whole thing using ISE.
  5. 1 point
    And we were able to do a full simulation of the system, so we can find bugs on it.
  6. 1 point
    Hi Alvie, I'm building at the moment directly the s3e500 under papilio-one from your github without changes and I also run it on a Papilio-one with S3e500. So its correct that it's not LX9. After I get everything running on the one I want to move to the LX9. Tobias
  7. 1 point
    For more info see: https://www.llnl.gov/news/nih-taps-lab-develop-sophisticated-electrode-array-system-monitor-brain-activity The NIH project is a collaboration between LLNL's Neural Technology Group; the laboratory of Loren Frank at University of California, San Francisco (UCSF); Intan Technology; and SpikeGadgets. Housed at the Center for Bioengineering, the Neural Technology Group will work with UCSF researchers to design and build electrode arrays that can record hundreds to thousands of brain cells simultaneously. Their goal is to develop 1,000-plus channel arrays that can eventually be expanded to 10,000 channels. These arrays will use new microchips designed at Intan and will send data to a system developed at SpikeGadgets. UCSF will coordinate these efforts and test the technologies. The arrays will penetrate multiple regions of the brain without interfering with normal functions during the experiments, allowing for detailed studies of brain circuits that underlie behavior. "This collaboration combines the engineering talent of LLNL with UCSF's expertise in neural recording and modulation systems, and the design and programming skills of Intan and SpikeGadgets," Frank said. "The result will be a system that will help us understand how different brain areas communicate and carry out complex mental functions."
  8. 1 point
    And I happen to work on a system that samples up to 1024 analog signals each 16-bit at 30 kHz sampling rate using up to 16 ADCs, each with a 64 ch mux All done with an Spartan6 LX16 and streaming the data out using a TMDS link (i.e. like HDMI but just clock and data) at 78.6 MB/s. using regular HDMI connectors and cables. For something like this you definitely need an FPGA. Here is a picture of a 640 ch system. FPGA board to the right with micro-HDMI connector for power and data, 5 ADC boards in the middle, each with 2 ADCs (i.e. 128 ch each), and LVDS terminator board to the left. The ADCs are connected to the FPGA using SPI with LVDS signaling (CS, CLK, MOSI, 16x MISO).
  9. 1 point
    Hi Im new to FPGA but have one question: Concerning Commodore MOS chips Is there open source for: 1351 Mouse Controller C64/C128 Ram chips REC memory controller SID: 6581,6582,8580 last known revisions? The last item is: I have heard that CBM MOS chips could possibly be redone using xilinx using PLD but its difficult but would any of the Papilio code still work with Xilinx software? Is there any open source for anything like the CBM MOS 1351 controller chip. (1351 was CBM Mouse, worked in Joystick Mode and Proportional mode). Other controllers wont work because the 1351 somehow worked along with the SID Oscillator, without that it wouldn't work. I hope I asked this in the right forum so any help is appreciated. Thank you, Terry Raymond
  10. 1 point
    Felix thank you very much, the application works and i managed to program it. John thank you for the explanation! Thank you guys' you're the best!
  11. 1 point
    it works. Using this Source and the Device source: http://www.macronix.com/Lists/ApplicationNote/Attachments/1148/AN0245V2%20-%20Using%20Macronix%20Serial%20Flash%20with%20Xilinx%20iMPACT%20Tools.pdf part: N25Q64
  12. 1 point
    @Jack - maybe we need to make testbed files for the p500 like i did for the pduo ? @island_peter - if you want to send your p500/arcade megawing to me i can test it for you ( i live near wiesbaden ) but as jack said, RomVault - Papilio Edition is a good way to test since it comes with a few free games and it loads them with just 2 clicks.
  13. 1 point
    Heh, "pay $10 more OR we will solder the connectors to the wrong side" Anyway, Zynq could be an interesting chip for the future. On a "fun" scale, Xilinx ISE is about the same as DIY dental surgery. Maybe Vivado improves on that...
  14. 1 point
    Its true all logic compilers are bad at producing relevant error messages and can lead users on a wild goose chase, the most common message being 'its broken and I am not telling you why'
  15. 1 point
    hehehehe, I thought the same thing myself when I first saw the name. Not sure I would have called an electronics board after a project that ended in flames myself.
  16. 1 point
    Please forgive this act of thread-necromancy. I thought it would be helpful to append a brief HOWTO for current Linuxes. Thanks, works like a charm after adapting playtime a bit to work on 64bit Linux Systems. In modern x86_64 Linuxes, remember to do the following first: Download the FTDI linux drivers (64bit or 32bit, depending on your system) from http://www.ftdichip.com/Drivers/D2XX.htmCopy over the headers:sudo cp ftd2xx.h WinTypes.h /usr/include/copy over the libraries to the correct location and create standard abbreviated links:sudo cp build/x86_64/libftd2xx.so.1.1.12 /usr/lib64/sudo ln -s /usr/lib64/libftd2xx.so.1.1.12 /usr/lib64/libftd2xx.so.1.1sudo ln -s /usr/lib64/libftd2xx.so.1.1.12 /usr/lib64/libftd2xx.so.1sudo ln -s /usr/lib64/libftd2xx.so.1.1.12 /usr/lib64/libftd2xx.soor if you are still using a 32bit kernel: sudo cp build/i386/libftd2xx.so.1.1.12 /usr/lib/sudo ln -s /usr/lib/libftd2xx.so.1.1.12 /usr/lib/libftd2xx.so.1.1sudo ln -s /usr/lib/libftd2xx.so.1.1.12 /usr/lib/libftd2xx.so.1sudo ln -s /usr/lib/libftd2xx.so.1.1.12 /usr/lib/libftd2xx.sochange the library to be used to the proper 64bit-lib on x86_64 in playtag/cables/ftdi/d2xx_wrapper.pyif windows: libfile = 'ftd2xx' loader = ctypes.WinDLLelse: libfile = '/usr/lib64/libftd2xx.so' loader = ctypes.CDLL if not os.path.exists(libfile): libfile = os.path.join(os.path.dirname(__file__), 'libftd2xx.so')If you are using ftdi-spi or ftdi_sio, you will now run into# sudo python tools/jtag/xilinx_xvc.py ftdi 0FTDI Driver error in function FT_Open: FT_DEVICE_NOT_OPENED (3)Thus, remember to unload the relevant kernel module first: sudo rmmod ftdi_sioHave fun and thank you, mkarlsson!
  17. 1 point
    Thanks everyone for the replies. Sorry to make you wait. It turned out to be my logic analyser was not keeping up. I went out and got a Digilent CMod S6. This board runs at 8MHz. After loading the same exact same code, the wave form came out as expected. I then did some research and loaded up the papilio pro with a DCM that cuts the speed down to 8MHz. The papilio pro works like a champ also. After some frustrating math and and trying to figure out how the world works, it turns out the 62.5ns pulse width combined with the slight difference in speed between the oscillator of the board and the logic analyser caused a rolling variation of just enough for the samples to catch the pulses for a few ticks and then miss for a few ticks. A lesson learned indeed. Some notes: Yes, I had a reset and the counter was initialized. All the extra trimmings were in the tutorial code. But when the results were not as expected, I wanted to remove as much as possible while trying to troubleshoot the issue. My logic analyser is the Saleae Logic (the first one). It only works reliably up to 16Msps on my pc. I thought 16Msps would be good enough, but after this adventure, I think I can talk my wife into letting me get one of the new models Thanks again, and please forgive my noobness. Gotta start somewhere.
  18. 1 point
    Rewiring and JTAG are outside my expertise, sorry. But I will note that according to the Papilio One Hardware Guide (http://papilio.cc/index.php?n=Papilio.PapilioOne), JTAG on this board already operates between 2.5V and 3.3V levels. It says the FTDI chip is 3.3V while the Spartan 3E's JTAG port is 2.5V. So maybe the problem is something else?
  19. 1 point
    It has a little help from a small, cheap CPLD (not many GPIO on the module), but otherwise yes, ESP8266 is driving everything. You can buy ESP8266 with ceramic antenna for about $2.5 each, in small quantities. Google for ESP-07. http://www.aliexpress.com/item/10pcs-ESP8266-serial-WIFI-model-ESP-07-Authenticity-Guaranteed-WIFI-module/32264981572.html
  20. 1 point
    IMO the biggest challenge facing FPGA development boards is cost. A Raspberry Pi 2 or ODROID-C1 is US$35 for a desktop-capable quad-core ARMv7 with 1 GB RAM, quad (or more) USB 2.0, and Ethernet. The cheapest Spartan-6 board I have seen from a reputable vendor is about US$70, twice as much. I had hopes for the Hackaday Arduino-Compatible FPGA board when it was first announced at US$50, but now it's up to US$70. US$35 is a great price point, because it's at a level that a hobbyist can buy without spousal approval and something students can afford. US$25 would be even better for an FPGA board. If you look at Spartan-6 LX9 pricing, it's not the chip cost. The problem is that FPGA boards aren't popular enough to manufacture in 10K or larger lots, like Raspberry Pi. The fact that there are so many different FPGA boards diluting an already small market makes the problem worse. So I would recommend designing an FPGA board that really drives the price down. I really like the Butterfly Platform that Jack posted upstream. Very simple board, with just an FPGA, bypass caps, and connectors. Spartan-6 is nice because you only need 3.3V and 1.2V -- you don't need 2.5V like the Spartan-3E. While I like having an FT2232H on board for programming, the fact is that those chips are pricey. For US$15 you can get an Adafruit FT232H breakout board which makes a dandy JTAG programmer, and you can use it for all your FPGA boards. The other big challenge is the steep learning curve of vendor FPGA software, but a number of us are working on that with various approaches. If it the software was a lot easier and there was a really cheap board we could help a lot of new FPGA users get started. JMO/YMMV
  21. 1 point
    the bcr2000 control sounds great! I also have both a bcr and a retrocade and can help you test it.
  22. 1 point
    Although TI documentation is far from the best out there Search for 'sprug04a'. Anyway, the implementation will be similar, but not exactly the same. I don't want to do a clone, for obvious reasons. Alvie
  23. 1 point
    Built two boards last night - one was trashed due to a misaligned HDMI connector, the other is looking OK. Haven't powered it up yet! Only problem so far is that the HDMI connector holes are a little bit too big... and yes, I also need to get some nice clean solder for attaching the pins, not my fifteen year old through-hole stuff!
  24. 1 point
    Assuming the need to go to multi-layer for the BGA part, that looks like it will be a very expensive board. You might look at a part such as the XC3S500E-4PQG208I which is in a 208 pin PQFP package. The FPGA is a bit more expensive but the PCB will be a fraction the cost if you can keep it to 2 layers. Also at least when it comes to Seeed, the cost of the board increases rapidly with size. 5cm * 5cm max is around $1/bd, 10cm * 10cm max is $2.50/bd, while the next size up, 15cm * 15cm max is close to $9/bd. If you can manage to keep it within 10cm square then the bare boards are ridiculously cheap.
  25. 1 point
    Latest code for windows and linux32 can be found here: http://pipistrello.saanlima.com/index.php?title=Arduino-1.5.2_on_Pipistrello