Leaderboard


Popular Content

Showing content with the highest reputation since 10/02/2014 in all areas

  1. 2 points
    Original version of game was running on PIC18F6622 and Dingoo A320. Now it's running on Papilio One 500K + Arcade Megawing. I've used the ZPUino soft processor which is realized by Xilinx Spartan-3E FPGA. VGA signal is also generated by the FPGA. The game can be played with integrated buttons of Arcade Megawing or with Atari/Commodore joysticks. I've used a QuickShot II Plus (SVI-102 Plus) joystick in the video below: Demo Please, use the .bit file included in the ZIP. Otherwise buttons and joystick are not working properly. sometris_v121.zip
  2. 2 points
    This is a library for Designlab and Papilio Duo. The decoder module can have up to 4 encoders. For example 4 wheels on a mobile robot platform. Optionally this can be use with a PID regulator for controlling current position, velocity, and direction of an object. - The shown pins are totally optional - By default the Avr chip is disabled Download: Quadrature_decoder.zip
  3. 2 points
    Or any other Xilinx FPGA board with an FTDI chip with MPSSE-engine connected to the JTAG pins (like Pipistrello but not Mojo or Saturn). This is using the xilinx virtual cable driver. Playtag is written by Patrick Maupin. Steps: 1) you need python 2.7 installed. Get it here:http://www.python.org/getit/ 2) unzip the attached zip file playtag.zip somewhere on your computer 3) open a cmd-window and cd to <playtag>\tools\jtag 4) connect your Papilo board to the computer 5) type xilinx_xvc.py ftdi, this will report the available FTDI ports.You should see the A and B ports of the Papilio board (see image). 6) type xilinx_xvc.py ftdi 0, this will start the xilinx virtual cable server on the A port of the Papilo board 7) you can now use impact and chipscope etc. by selecting the xilinx_xvc plugin. Use this plugin settings: xilinx_xvc host=localhost:2542 disableversioncheck=true See attached images and zip file. Do a google-search for xilinx_xvc for more info on how to use the virtual cable driver. Magnus playtag.zip
  4. 2 points
    Once you get it gojng, rather than using a sine wave, why not try a GPS gold code? ( or something similar to one) It is a pseudo random bit stream that is quite long. When you correlate with an external signal you can get a really precise phase lock. This time to phase lock is what gives the long time to first fix of a GPS as it trys all the different alignments, but once locked it is very solid, even though the power levels of the signal is well below the noise floor and mixed up with all the other GPS birds. By having g a real time clock on the GPS the time to first fix is improved as the GPS knows where to start hunting. Also, I believe that most GPS units have a one bit DAC, so maybe a bandpass filter and to compare against the long term average is all you need?
  5. 1 point
    Hi, I just got started with Papilio Pro last week (side note: Great work with the papilio family and wings.. Im really excited about the board's potential). The Pro was my first entry to the papilio line. I was mostly able to figure out how to get the board running and programming. But, many of the instructions/downloads on the papilio website are either outdated or directed towards Papilio One, so getting started took about 4 hours longer than I expected. I thought I'd put together a list of links and instructions for problems I encountered along the way so that perhaps others starting with the Papilio Pro could have something up-to-date (well, as of April 2013, that is): 1. Windows FTDI Drivers: I had some real trouble getting the Papilio recognized as both a USB and a virtual COM port. For my problem, the device was ALWAYS recognized on Windows-- even when I did not have the Gadget Factory drivers installed. And it never showed a virtual COM port. Troubleshooting suggests using a different cable, or editing the device properties. Apparently in my situation, the Papilio was recognized as an FTDI device first and was not using the Gadget Factory drivers. My solution: Download the FTDI CDM Uninstaller. Using FTDI's USBView utility, find the Device Vendor ID and Product ID. Use the CDM Uninstaller to uninstall the FTDI drivers for the Papilio. After plugging and replugging, Windows recognized a virtual COM port. I could also connect through putty and see the default ASCII table output which was apparently the factory default program. 2. Getting Started Bitfile: http://papilio.cc/index.php?n=Papilio.GettingStarted It appears as though the getting started website (as of April 5 2013) does not include the getting started bit file for Papilio Pro. In my beginner state, I assumed this website would have the materials I needed, so I fumbled around trying to use the Papilio One 500K bitfile. After a while, I realized it certainly doesnt make sense to try to use the Papilio One bitfile, especially since the Papilio Pro uses a completely different FPGA. I dont think I've found a replacement for the "Getting Started" bitfile for the LX9 yet. 3. Papilio Loader: As with the bitfiles, the Papilio Loader GUI on the Getting Started Page is out of date (it downloads v1.7). According to a forum discussion around December 2012, the Papilio Loader was modified to support the Papilio Pro. Download the Papilio Loader GUI specifically from the Downloads webpage (this should be version 2.1 or later): http://forum.gadgetfactory.net/index.php?/files/category/2-papilio-fpga/ 4. ZPUino Core and Loader: I think the official ZPUino download page is a little out of date for Papilio Pro. It looks like the papilio website ZPUino getting started guide is out of date too- It uses an old version of the IDE and does not include links for the Papilio Pro bitfiles. Instead a forum post indicates the RetroCade installer works with the Papilio Pro. So, to get the ZPUino to work, download the Retrocade Synth Windows Installer from the Download Page. Use the bitfile ZPUIno_SOC/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit to program the Pro. The installer should also include a version of the Arduino GUI which includes a board option for ZPUino on Papilio Pro (LX9). 5. Intro to FPGA Book: With a functioning Papilio Loader and a ZPUino core/ GUI, I was basically good to go with the Intro to FPGA E-book. I also installed the Xilinx toolchain as instructed. No issues there. I'm looking forward to generating and programming with my own bitfiles shortly. It would, however, be nice to have an updated Xilinx webpack quickstart page: http://papilio.cc/index.php?n=Papilio.XilinxISEWebpackQuickStart. EDIT: I installed the wrong Xilinx tools at first. The default link inside the Intro to FPGA E-book now leads to the Xilinx Vivado suite, which doesnt support the Spartan 3 or Spartan 6 series. Instead, make sure to download and install the ISE Design Suite. 6. Papilio Arcade: I also tried the papilio arcade wing. Just make sure to download the correct LX9 bit files from the github https://github.com/GadgetFactory/Papilio-Arcade I havent looked at the AVR8 softcore processor. This is on my list to test with the Papilio Pro, along with some other fun things (SoC editor is on the horizon too). Like I said, Im a big fan of the board. Overall, it looks to be a really great FPGA. I do want to see the usability/ learning curve get to the Arduino level, and it helps to have a good getting started procedure for all boards. Hopefully this helps another beginner in the same situation. Thanks for all the work so far! EJ
  6. 1 point
    Hi all, I know it will sound stupid, but anyone knows if I have to enable something in ISE (14.7) to get the symbol manager? I followed the tutorial on the learning site but, after I loaded the example project, the Tools dropdown ends with "Smart Xplorer" and there are no other options as on the screenshot..... Where am I missing the point? :-D Thanks!
  7. 1 point
    Ok, first a few definitions: USB High-speed = 480 Mb/s transfer rate -> this is what you want USB Full-speed = 12 Mb/s transfer rate USB Low-speed = 1.5 Mb/s transfer rate Most boards (like Arduino, Papilio One, Papilio Pro, Mojo) only has Low-speed or Full-speed USB I/O so not good for your application. The most common way to get USB High-speed device support is to either use an FTDI FT2232H chip or a Cypress FX2 chip. Cypress FX2: I have very limited experience with the Cypress FX2 chip so others might have to chime in here. The aes220 board above uses the Cypress FX2 chip so that sounds like a good candidate. There are many other boards that's uses the FX2 for USB (like Opal Kelly XEM6002, boards from KNJN and many more). Just do a google search on "FPGA FX2". FT2232H: To get the max data rate (~28 MB/s) from the FT2232H chip you need to use synchronous FIFO mode which is only available on the A port, but most boards with this chip (like Papilio DUO, Pipistrello, Saturn and miniSpartan6+) uses the A port for JTAG so no Synch FIFO mode. Pipistrello, Saturn and miniSpartan6+ have the B port hooked up for async FIFO mode, this will get you at most 9 MB/s. Papilio DUO only has the B port MPSSE signals hooked up to the FPGA so at the most you can get is the 30 Mb/s MPSSE data rate on the DUO. The only board that I know of that has an FT2232H chip hooked up for Sync FIFO mode is the version 1 of the Pipistrello board, it can do 28 MB/s transfer rate. Another alternative is to get a board with USB 3.0 support (a.k.a. USB SuperSpeed) using the Cypress FX3 chip, like Opal Kelly XEM6310, it can do > 340 MB/s... Hope this helps, Magnus
  8. 1 point
    This is not correct, the DUO does have a USB 2.0 chip on board (FTDI 2232H) and it can do up to 30 Mbits/sec in MPSSE mode and up to 12 Mbits/sec in serial mode. Not as fast as you want but faster than 3 Mb/sec. Magnus
  9. 1 point
    I don't think the Papilio Duo has USB. There is a USB serial chip as described here (http://papilio.cc/index.php?n=Papilio.PapilioDUOHardwareGuide#PProUSB). So up to 3MHz via serial. I think you'd need to connect a USB2 chip to the GPIO to achieve this. I've had success with usbhostslave, usb chip + some resistors, but that is only 1.1 speeds.
  10. 1 point
    We're talking in context of the Papilio though, the Pro has a Spartan6 LX9. I just looked up the specs and it seems it has more BRAM than I had remembered, 32 blocks of 18Kb which works out to 72kB so that should be enough depending on whether it uses any other RAM or ROM. If it uses that many slices of the LX45 then there's no way it's gonna fit though, unless the high usage is due to using slices instead of BRAM for RAM.
  11. 1 point
    One thing about clock generation is that using a logic signal as a clock (as in 'rising_edge(tap)' above) is discouraged in FPGAs. As I understand it (which is limited, I'm still sort of a newbie) one of the problems is: Logic is sometimes "glitchy" (temporary bogus output values that last less than a clock cycle, and thus wouldn't matter, unless you use them as a clock). Another has something to do with routing and timing analysis. One alternative, if you want to run part of your circuit slower than your clock, is to use a clock enable. Suppose, for example, "CLK" is your clock and "en" is a signal that's HIGH for one out of every five clock cycles. Then you'd do the following: if rising_edge(CLK) and en = '1' then do <= stuff; end if; (Please pardon any syntax mistakes, I mostly use Verilog and am unfamiliar with VHDL.) The FPGA hardware has special support for handling this sort of thing.
  12. 1 point
    Hi All, A couple of years ago, I stumbled across a minimalist, interpreted programming language, created by Ward Cunningham - wiki pioneer. He called it Txtzyme - a concatenation of text and enzyme, and suggested that it could boost creativity. What it is, is a tiny interpreted language, where a single ASCII character is interpreted as an instruction, and causes a block of associated C code to be executed. It is so compact, it can be condensed into about 90 lines of Arduino C code. However, what it provides, is a powerful means to command the hardware of a microcontroller, just using a few characters sent over a serial port. Essentially it is a low level language for exercising new hardware. I took Ward's simple interpreter and extended it, to create a programming tool, that I call SIMPL. It borrows heavily from some of the minimalist ideas, first used 40 years ago by Chuck Moore's FORTH and the various TinyBasics used in the mid-1970s for some of the early 8 bit systems. To cut to the chase, I now have SIMPL running on ZPUino, on a Papilio Duo with Logic Start Shield. I can turn LEDs on and off with a few snippets of interpreted code, run LED chasers or synthesize musical tones. I'm currently trying to compile about 2 years of experimentation into a concise document. In the meantime - if you want to play with SIMPL - the raw sketch is up her on this github gist. https://gist.github.com/monsonite/97730b0456762da20a98 I'd appreciate comments and feedback. Have fun Ken B London
  13. 1 point
    You may also want to break it down into smaller chunks, that you can put together into a working project. First start with turning on some LEDs, then.... a: Can you receive a single byte from the PC and display it on some LEDs? b: Can you generate a VGA test picture? c: Can you make a memory and play back a pattern onto LEDs? Then you can build a+b: Can you store bytes from the PC into a memory? b+c: Can you display a picture from memory? Then finally a+b+c: Taking data from the host, storing it in memory, and displaying it on the screen.
  14. 1 point
    That's the spot sorry not much help ATM but it's almost 10pm and I work very early tomorrow. I will reply back on wed after I have a chance to look into it.
  15. 1 point
    I've just finished testing my LED driver PCB - 8 channels, each driving two constant current outputs (well, sinks actually). Loaded with 50 ohm sense resistors it gives 13mA per channel. 33 ohm will give 20mA. It is using discrete transistors to allow for higher power dissipation - maybe up to 300mW per channel, so should survive a hard short in in LED chains that that run at up to 15V. If anybody wants a PCB just ask... I can send it air post so you might just be able to use it for your Christmas tree lights
  16. 1 point
    I like it :-) For the electronics guys, I also like the "Have you ever played around with solderless breadboards and little ICs? - and FPGA is equivilent to a breadboard the size of a somewhere between a garage and a basketball court, all covered in digital ICs, and a thousand eager minions ready to do the tedious wiring for you".
  17. 1 point
    Basics, back to basics.... Bootloader, loads app from SPI flash, which in turn uses SD card and bootstraps application from there. XThunderCore Boot Loader v0.1 (C) 2014 Alvaro LopesTesting memory: OK, connecting to SPI flashSPI Flash Identification: 0x00BF258DProgram size: 0x000052C7, CRC 0x0000Signature: 0x310AFAD5Target board: 0x00000000Loading: Checksum: 0xDCB4446F, mem 0xDCB4446F doneStarting application.Registered console dev:serial0STDIO base registered in console dev:serial0Starting....SD Card initialisedApplication found, size 445480Application read (445480 bytes), starting....Registered console dev:serial0STDIO base registered in console dev:serial0French version DOOM 2: Hell on Earth v1.10 V_Init: allocate screens.M_LoadDefaults: Load system defaults.Z_Init: Init zone memory allocation daemon.W_Init: Init WADfiles. couldn't openError: W_InitFiles: no files foundNow, need to port SD library to work with the application/zposix interface. Should be fairly easy. Alvie
  18. 1 point
    @Chris_C: I think the point of the flancter is not the counting (that's just given as an example) but handling input pulses that are so short that you can't sample them with your clock. I gather that crossing clock domains, or dealing with asynchronous (clockless) data, is quite a pain. That's what would make the flancter useful. Re synthesis: I've also heard that what's synthesizable on one FPGA might not be on another; or even with a different synthesis tool. Another reason I can think of that you might want to simulate something you can't synthesize, is if half your circuit is synthesizable RTL (your circuit in all its glory) and the other half is a non-sythesizable behavioral model. Like perhaps that second part isn't done yet; or it's something you're going to buy and this is just a sample; or it's an off-FPGA component on your board. Re simulation: My simulator of choice is Icarus Verilog. Free, relatively capable, command line oriented. But so far I seem to be using it more for debugging than testing. Also a quick (if over-lenient) syntax checker.
  19. 1 point
    Built two boards last night - one was trashed due to a misaligned HDMI connector, the other is looking OK. Haven't powered it up yet! Only problem so far is that the HDMI connector holes are a little bit too big... and yes, I also need to get some nice clean solder for attaching the pins, not my fifteen year old through-hole stuff!
  20. 1 point
    Yeah the subscription is only $50/year for the electronic edition (pdf download). I've been reading CC since I was a young whipper snapper, I have a full pdf collection back to issue 1.
  21. 1 point
    Hi guys, I just wrote a small C++ application (text-mode) that can compute the two primary configuration values for PLL (multiply and divide), given an input clock speed and the required speed. Since some of these are not possible directly using a single PLL, the application also scans for a dual-chained PLL approach, where the output from the first PLL is fed into the input of the second PLL. These two parameters are enough for you to get a working PLL with your desired frequency. Source code and prebuilt windows .exe available at: http://alvie.com/zpuino/downloads/pllscan/ Enjoy Alvie
  22. 1 point
    I could not found your code at here: http://www.rulecity....er-17Feb2013.7z. Please let me get source file for SDIO studying.
  23. 1 point
    How are the SID filters controlled? I don't see controls for them in the dashboard, are they mapped to CC messages?
  24. 1 point
    I decided to also port the Demon 3.07 verilog code to Papilio_One. This version is identical to the code running on the OpenBench Logic Sniffer board except for using 32MHz oscillator and using serial@115200 instead of SPI. It supports both meta data and input pin data query. The full XISE project can be found here: http://www.saanlima.com/download/Papilio_One/Papilio_One_OLS_3.07.zip 250K and 500K bit files are attached. Let me know if you notice any strange behavior. View attachment: logic_sniffer_P1_250K.bit View attachment: logic_sniffer_P1_500K.bit
  25. 1 point
    Assuming the need to go to multi-layer for the BGA part, that looks like it will be a very expensive board. You might look at a part such as the XC3S500E-4PQG208I which is in a 208 pin PQFP package. The FPGA is a bit more expensive but the PCB will be a fraction the cost if you can keep it to 2 layers. Also at least when it comes to Seeed, the cost of the board increases rapidly with size. 5cm * 5cm max is around $1/bd, 10cm * 10cm max is $2.50/bd, while the next size up, 15cm * 15cm max is close to $9/bd. If you can manage to keep it within 10cm square then the bare boards are ridiculously cheap.