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Showing content with the highest reputation since 05/12/2014 in all areas

  1. 2 points
    Original version of game was running on PIC18F6622 and Dingoo A320. Now it's running on Papilio One 500K + Arcade Megawing. I've used the ZPUino soft processor which is realized by Xilinx Spartan-3E FPGA. VGA signal is also generated by the FPGA. The game can be played with integrated buttons of Arcade Megawing or with Atari/Commodore joysticks. I've used a QuickShot II Plus (SVI-102 Plus) joystick in the video below: Demo Please, use the .bit file included in the ZIP. Otherwise buttons and joystick are not working properly. sometris_v121.zip
  2. 2 points
    This is a library for Designlab and Papilio Duo. The decoder module can have up to 4 encoders. For example 4 wheels on a mobile robot platform. Optionally this can be use with a PID regulator for controlling current position, velocity, and direction of an object. - The shown pins are totally optional - By default the Avr chip is disabled Download: Quadrature_decoder.zip
  3. 2 points
    Or any other Xilinx FPGA board with an FTDI chip with MPSSE-engine connected to the JTAG pins (like Pipistrello but not Mojo or Saturn). This is using the xilinx virtual cable driver. Playtag is written by Patrick Maupin. Steps: 1) you need python 2.7 installed. Get it here:http://www.python.org/getit/ 2) unzip the attached zip file playtag.zip somewhere on your computer 3) open a cmd-window and cd to <playtag>\tools\jtag 4) connect your Papilo board to the computer 5) type xilinx_xvc.py ftdi, this will report the available FTDI ports.You should see the A and B ports of the Papilio board (see image). 6) type xilinx_xvc.py ftdi 0, this will start the xilinx virtual cable server on the A port of the Papilo board 7) you can now use impact and chipscope etc. by selecting the xilinx_xvc plugin. Use this plugin settings: xilinx_xvc host=localhost:2542 disableversioncheck=true See attached images and zip file. Do a google-search for xilinx_xvc for more info on how to use the virtual cable driver. Magnus playtag.zip
  4. 2 points
    Once you get it gojng, rather than using a sine wave, why not try a GPS gold code? ( or something similar to one) It is a pseudo random bit stream that is quite long. When you correlate with an external signal you can get a really precise phase lock. This time to phase lock is what gives the long time to first fix of a GPS as it trys all the different alignments, but once locked it is very solid, even though the power levels of the signal is well below the noise floor and mixed up with all the other GPS birds. By having g a real time clock on the GPS the time to first fix is improved as the GPS knows where to start hunting. Also, I believe that most GPS units have a one bit DAC, so maybe a bandpass filter and to compare against the long term average is all you need?
  5. 2 points
    There is plenty wrong with VHDL and Verilog but I have to say the biggest problem I (and I think many people from a programming background) have is the business of thinking in parallel. Not just the idea that things like assignments take time and aren't instant but things like the fact that (except for power in some cases) it's actually not worth doing conditional evaluation of something, you can evaluate it every clock at no extra cost, in fact you can evaluate hundreds of un-needed things for free just in case they are relevant to a given cycle. Not sure a language can help much with that. There is simply a gap between the conceptual model of programming and the reality of FPGA.
  6. 2 points
    Hi, not every pin can function as clock input. See here http://www.xilinx.com/support/documentation/user_guides/ug385.pdf page 30, search for "GCLK" in the name. Now did you know that there are PLLs inside the FPGA? It takes 2 min of work (maybe a bit more if you do it the first time) to run the core generator and turn the existing 32M clock into 20 MHz or whatever you like. It's one of the most useful features, IMO, in everyday use.
  7. 2 points
    ever heard of "paralysis by analysis"? My advice still stands: Don't try to buy the "best" or the "right" board. Just get any cheap board, spend two working weeks and learn to make that LED blink.
  8. 1 point
    This is not correct, the DUO does have a USB 2.0 chip on board (FTDI 2232H) and it can do up to 30 Mbits/sec in MPSSE mode and up to 12 Mbits/sec in serial mode. Not as fast as you want but faster than 3 Mb/sec. Magnus
  9. 1 point
    (In the meantime, anyone using VMWare that can't boot DesignLab -- go into VMWare's sharing settings and turn off sharing. Sharing makes your Windows home folder read-only, which the Arduino version of java doesn't like when it's trying to enumerate the serial devices.)
  10. 1 point
    Jack, so I ran the testplan. It did solve the 2 ports problem, now I only see 1. However the sketch still wont upload to the zpuino with the same message as before (see attached)
  11. 1 point
    You have several defines you can use. On all boards, ZPU is defined. On 2.0 boards, ZPU20 is also defined. You can also check for specific boards. Foe example, __ZPUINO_PAPILIO_DUO__ is defined in Papilio DUO boards, and __ZPUINO_PAPILIO_PRO__ in Papilio Pro boards. You can inspect platform.txt and boards.txt for ZPUino, as shipped in DesignLab, for more details: https://github.com/GadgetFactory/DesignLab/blob/master/hardware/zpuino/zpu20/boards.txt https://github.com/GadgetFactory/DesignLab/blob/master/hardware/zpuino/zpu20/platform.txt Alvie
  12. 1 point
    You may also want to break it down into smaller chunks, that you can put together into a working project. First start with turning on some LEDs, then.... a: Can you receive a single byte from the PC and display it on some LEDs? b: Can you generate a VGA test picture? c: Can you make a memory and play back a pattern onto LEDs? Then you can build a+b: Can you store bytes from the PC into a memory? b+c: Can you display a picture from memory? Then finally a+b+c: Taking data from the host, storing it in memory, and displaying it on the screen.
  13. 1 point
    Here's how to read a pot, using only two resistors and a capacitor: http://hamsterworks.co.nz/mediawiki/index.php/Cheap_Analogue_Input It is based around the technique used for the joystick interface on the Apple II. Only downside is that you need to calibrate the the limits - but perfect as a paddle interface for a game of Pong, where you could just remember the max & min readings.
  14. 1 point
    you have Great video Channel on YouTube thank you very much wish you upload more video Tutorials about FPGA , VHDl , and Papilio in the Future MY REGARDS
  15. 1 point
    well, to send a signal through USB and a fiber optic cable, you can even take a simple USB-to-serial chip: https://www.sparkfun.com/products/9873 then a LED on one end and a photodiode at the other end, going into a 2nd USB-to-serial chip (or even into the receiver section of the same chip). There is no need for microcontrollers, FPGAs etc. But this won't earn you any credits in a computer science course, it's just basic electronics tinkering. And no, driving fiber optics with a simple UART is not how it's done in real life even if the bits will go through just fine if you lowpass filter the detector to 0.01 % of its designed bandwidth.
  16. 1 point
    You should maybe discuss this project with a university supervisor, set up some realistic targets and put you on the right track with the "architecture". Generating a 12 Mbit/s signal is trivial, simply put it onto a block ram. It can be as simple as the following (this is quick-and-dirty, haven't actually compiled it) module myPatternGenerator(input wire clk, output reg outPos, output reg outNeg); reg [255:0] sequence = 256'b01001001010110111011...; always @(posedge clk) begin outPos <= sequence[255]; outNeg <= !sequence[255]; sequence <= {sequence[254:0], sequence[255]}; end endmodule I'd expect clk can go up to maybe 170 MHz, higher with careful coding. You can generate it inside the FPGA from the oscillator on the FPGA board. Then delay it by a variable amount inside the FPGA. Analyze synchronously within the same circuit, and here it starts to get interesting. You can test this with a simulator, i.e. "iverilog" and "gtkwave", if you like. Or use "isim" that comes with the Xilinx tools.
  17. 1 point
    I have often thought about a USB 1.0 stack (12Mb/s), based on the virtual USB HID for Arduino that you can set up with a couple of Zeners and a few resistors (http://www.practicalarduino.com/projects/virtual-usb-keyboard) However, even that is too hard for me to comtemplate moving to a FPGA, - every time I start to attempt it I feel like I am pounding my head against a brick wall.
  18. 1 point
    >> I was thinking it's easy to learn FPGA and then make your idea real by using it It is not. It is 1000x harder than it looks. You would use a "virtual com port", send serial data from PC to FPGA. This is relatively easy. Even easier, implement a pseudorandom generator to create the data. But, sorry for being direct, you're totally in over your head. Proposal: Why don't you buy some cheap low-end FPGA board. Papilio is fine, so is any other, just don't try to anticipate what you think you need. What you really need is one LED and two months hard work. Learn to make it blink, control it through the PC (USB-serial port and UART). When you can do that, you'll be in a much better position to judge the task at hand. It would be realistic for an experienced engineer but not if you're starting from square one. PS you don't actually have to buy it, just get the design tools and learn to use them (and get used to simulate: Hardware just tells you "it doesn't work". Not "why"). The tools are neither beginner- nor user friendly, takes a lot of patience.
  19. 1 point
    Thanks! I had to: dpkg --add-architecture i386apt-get updateapt-get install ia32-libsnow it seems its compiling the sketch correctly. Will try it with my papilio but I guess it will be probably ok.. thanks again alvaro!
  20. 1 point
    This: apt-get install ia32-libsshould do the trick. If not, I can provide you 64-bit binaries.
  21. 1 point
    OK, I'm convinced enough to do it. The days of spinning rust are numbered.... I'm thinking that soon computer architectures will be reduced to a 64-bit memory space, with some of the space being true RAM and some being (cached) SSD/flash. Goodbye SATA, goodbye SAS, Strangly this is much like IBM's mainframe architecture....
  22. 1 point
    Hi, I am a contestant of digilent contest, and I need a feedback for my project. The project name is "Real Time Digital Circuit Design tool in FPGA with VGA interface" Short description: This project implements a digital circuit design tool, as the name says, in FPGA. The FPGA board is connected directly on a monitor and a mouse. The user should use this project to create a digital schematic, and he could check the output signals on a logic analyzer which is included in the project. Here we have two working modes: directly mode, using a mouse which is connected directly on FPGA board, and second mode, using PC. In second mode, user should use Xilinx ISE to create a schematic, and after executing a command, some data are transferred to FPGA via RS232 communication and the schematic is created automatically. FPGA part is implemented in VHDL and in second mode, the data prom Xilinx ISE schematic is processed with Visual Basic Script. You can watch on a example movie on the following link: Thank you!
  23. 1 point
    Jack, is BGA technology out of the question for the FPGA? If you could manage the CSG225 package, it is only $1 more than the TQFP option (digikey, unit 1), and would offer the possibility of having an LX16 option as well as LX9. If it is possible to route to some of the extra I/Os, you could stick with the x16 SRAM and not make any compromise there. If you could mange a CSG324 BGA, then LX9, LX16, LX25, LX45 are all possible. That would be great, even if most of the extra I/Os are not routed out. I realize that inspection of BGA soldering is probably an even bigger issue than the routing of it. At least with the routing, it is a one time problem and you know where you stand. Overall, I think SRAM is a lot more approachable than SDRAM design. On the other hand, some of the xilinx parts have integrated SDRAM controllers, paying attention to the routing and connecting the SDRAM to the right pins and making sure all the right traces have matching length, you get speed and capacity without too much pain.
  24. 1 point
    How are the SID filters controlled? I don't see controls for them in the dashboard, are they mapped to CC messages?
  25. 1 point
    Jack, I tried powering the board both through a high-quality powered USB hub and through a direct USB port on the machine. With both, the noise was clearly audible. When I used an external power supply, there was no issue. In a performance situation, there'd be no issue with using a separate power supply, but for development, the approach won't work. I'll try powering from an extra laptop tomorrow, just for another data point. I kind of suspect a ground connection issue, but I'm not much of an electronics buff. -Hans