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  1. Past hour
  2. Does it need any more information or explanation? I have 2MB SRAM on the DUO, but I can only use 25% of it (~500KB).
  3. Hi I'm working with Papilio DUO, Papilio DesignLab 1.0.8 and ZPUino SOft Processor Vanilla v2.0. I'm just testing how much RAM I can use in my sketch. For this reason I increase the size of an array (unsigned char). The sketch below with an array size of 501*1024 bytes is not running. The same sketch with an array size of 500*1024 is working fine. static unsigned char bufferRAM[501*1024]; void setup(){ pinMode(13, OUTPUT); Serial.begin(115200); } void loop(){ digitalWrite(13, HIGH); delay(100); digitalWrite(13, LOW); delay(100); Serial.print(bufferRAM[0]); Serial.println("Hello..."); } Compiler output: Binary sketch size: 515.216 bytes (of a 2.048.000 byte maximum) - 1.728 bytes ROM, 513.640 bytes memory, 25% used Der Sketch verwendet 1.576 Bytes (0%) des Programmspeicherplatzes. Das Maximum sind 2.048.000 Bytes. Globale Variablen verwenden 152 Bytes des dynamischen Speichers. What can be the reason? The Papilio DUO Hardware Guide website says: The ZPUino Soft Processor integrates the SRAM which gives your ZPUino sketches 512KB or 2MByte of code space! Thank you for your help!
  4. Last week
  5. CircleOne is a wireless charging power bank with portable, light, durable aluminum design. find us on Kickstarter and search CircleOne CircleOne on Kickstarter IMG_6136.mp4
  6. Hi, I stumbled up on this (ratter long but interesting video on "icesoc" ) I might give us some ideas
  7. Earlier
  8. Programming to FPGA SPI Flash not working

    Hi adamada, After programming the SPI flash, you need to power cycle (remove power and then connect power back again). Took me some time to figure out :-) --Anirban
  9. ISE Placement Error

    I see, that makes sense. Thanks, Thomas. --Anirban
  10. ISE Placement Error

    Hi Anirban, all pins in one so called IO Bank of a Xilinx FPGA share the same Vcc voltage. This means, that you need to assign them a IOSTANDARD with a compatible voltage. So you can for example mix LVTTL (which is 3.3V) and LVCMOS33, but not LVCMOS33 and LVCMOS25. I don't know the details of the Papilio One, but at the Papilio Pro which I use all IOBanks are connected to a 3.3V supply. Why the standard UCF for the Papilo One specifies the clock pin with LVCMOS25 I don't know. Thomas
  11. ISE Placement Error

    Hi, I am trying out the newbie example here: (plan to load design onto a Papilio One 250) Running synthesis gives this error: Starting Placer Phase 1.1 ERROR:Place:311 - The IOB clk is locked to site IPAD21 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed. The constraint file (downloaded from here) NET clk LOC="P89" | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns; When I change the IO type to IOSTANDARD=LVCMOS33, PnR completes without error. What could be the reason why 2.5V CMOS is not supported? Thanks Anirban
  12. On All of the 'Older OpenBench Logic Sniffer Versions' links are toast... the subdomain isn't responding; all I get are timeouts. I could probably get away with just the 3.07 core for the Cypress chip and run PulseView, but it'd be nice to have the full install just in case I'm missing something. I don't know that I need 3.06 core file, as I recall seeing on (EEVBLOG?) that the 3.07 core was fully functional and recommended over the 3.08 build.
  13. SDRAM controller for Papilio Pro

    Hi Sergey, without referring to the actual source code it is hard to understand to what version of the controller you refer to (especially the "simple" one). As you noticed Hamsters Website is offline, so there is no documentation anymore. What I remember from my mind is, that he developed several version of the controller, they differ in complexity of their state machines and their performance. The most basic one he wrote just executed every DRAM access isolated (with opening the row, opening the column, reading/writing and then closing the row and going back to idle state). This is very slow, because every access to the DRAM requires more than 20 clock cycles. The more advanced versions support back-to-back read/writes, which means that several sequential accesses to adjacent addresses of the DRAM can be run much faster. Actually the latest version of his controller is not really "huge", it is around 550 lines of code and it is well commented. To understand it, you should read the SDRAM chips datasheet it describes quite well how it works. Once you understand it, hamsters controller looks quite straight forward. You should consider using my version of it (see link above), it worked in several Papilio Pro designs right out of the box. I usually use a clock frequency of 96Mhz, believe me, it works. I'm sure the Alvies version in zpuino is equally proven, looking in the source code I think it is based on Hamsters "older" design. It requires two phase shifted clocks (which can easily by accomplished), while the 0.6 version creates a phase 180 degrees phase shifted clock internally with the help of a ODDR2 block. The shifted clock is required to compensate for the pcb trace delays and ensuring that the control and data signals are stable when the clock arrives at the DRAM chip ("setup and hold times"). The zupino variant with the extra clock is more complex, but maybe works over a wider clock frequency range, because the phase shift does not depend on the frequency, it keeps constant. I never tried different versions of Hamsters controller, this latest ensures for example that the Flip-Flops in the IO Blocks of the FPGA are used, this is very important for reliable operation. You can verify this in the "Design Overview /IOB Properties" Node in ISE: In Column "Regs" "IFF", "OFF" or both of them must be reported for Inputs/Outputs/Bidirectionals. Are you using the SDRAM Controller directly or do you have e.g. a Wishbone interface in between? Have you tried my advice and simulated the design?
  14. SDRAM controller for Papilio Pro

    Hello to all, Thank you very much for your advises. I was trying to understand both Hamster's SDRAM controllers (simple and extended (ZPuino one)). The last one seems to be quite difficult for understanding for me so far. Alvie, could you please give some hints why this huge controller is so... huge? I mean what are its advantages before the simple one? (sorry if my question seems stupid) I made some success with the simple SDRAM controller, though I still have some random misreads. Kind regards, Sergey
  15. SDRAM controller for Papilio Pro

    Hi, the latest version of Hamster Controller on his website did not work without a slight modification on the Papilio. Here is a corrected version, which works for me in several designs on the Papilio: The Fix is the "delay_line_length " parameter, which must be 5 for the Papilio. Clock frequency should be ~100Mhz. My version also has an "hold_row_open " parameter, which can improve performance in some applications (end reduce in others...). It holds the active row open until a different row or a refresh is needed. I also strongly recommend simulating the design, Hamster also has an sdram simulator (you can also get a slightly modified version here: You can also check with a simulation if your access to the controller works in the right way. If you like I can post a few simulation screen shots here to show how it should work. You should also install a bit file of a proven design, like socz80, Zpuino or for example: (this post contains a "monitor.bit" which you can upload into the Papilio. The boot monitor contains a DRAM test which can be started with the "T" command. It is just that you can verify that your Papilio Pro board has no hardware defect (unlikely but not impossible...) Thomas
  16. some updates needed

    it is in I also use windows 10 64b , the 2.12.28 version worked for me (first option) good luck!
  17. can you explain more how to do it ? step by step . its looks like not working for win 10 pro 64 bit . force shutdown and something i m getting others error .
  18. Download Error YAVGA

    Thanks james for the link . its a great help for me as i m looking this for long time and always the site is offline . better if someone will make a mirror link .
  19. some updates needed

    i am facing the same issue . but i dont know where is FTDI driver . Nadav can you please give me the driver link separately ? i m using windows 10 pro. Thanks in advance.
  20. SDRAM controller for Papilio Pro

    Try my (ZPUino) SDRAM controller. You can find here: It uses pipelined wishbone, so make sure you don't hold STB high after your request has been accepted. Also take a look at the PLL settings for it Any issue drop me an email at alvieboy at alvie dot com Alvie
  21. SDRAM controller for Papilio Pro

    SDRAM isn't something I'd recommend a newbie try to deal with. It is tricky, and further complicated by the fact that until read and write both work, nothing works. Starting with simpler projects is recommended. I can't point you to any examples meant for teaching, but here are some existing projects, which use the SDRAM, that come to mind; they might be informative. "socz80" at uses Hamster's SDRAM controller with a Z80 CPU. The "ZPUino" port for Papilio Pro also uses that controller, see and These might also be using different versions of the controller. I believe clock rate matters for this controller, ZPUino runs at 96MHz, socz80 at 128MHz; at much lower clock rates it won't operate right. I've found that anything on an FPGA requires a lot of debugging, it's just something you have to do.
  22. Hello, I'm a newbie in the FPGA, and I'm managing with the Papilio Pro Board. The problem is I can't make the SDRAM work correctly. I was trying to use the Hamster's SDRAM controller, and did as he describes, but I get weird results. First, sometimes it reads with random mistakes (though it might be a write problem, I don't know) Second, sometimes during sequential read it reads first 3-4 values the same and only then starts to increment address. Could you please advise some VHDL code example of how to explore the Hamster's SDRAM controller (or any other)? Hamsterworks wiki site doesn't work for some reason so I can't read his explanation once more... Kind regards, Sergey
  23. .bmm Problems

    Hello everyone I also have the same error. I understand the problem is related memory. but I am not getting how to find a way to get the path to the memory so it doesn't choke? ERROR:NgdBuild:989 - Failed to process BMM information ipcore_dir/microblaze_mcs.bmm INTERNAL_ERROR::45 - Memory allocation leak of 112 bytes at 0x06EC0A58 for a 'AddressMappingType' record. INTERNAL_ERROR::45 - Memory allocation leak of 58 bytes at 0x06E43E20 for a StrNew. INTERNAL_ERROR::45 - Memory allocation leak of 88 bytes at 0x06F41F08 for a 'AddressMapType' record. INTERNAL_ERROR::45 - Memory allocation leak of 40 bytes at 0x06E43D98 for a 'symbol_context' record. INTERNAL_ERROR::45 - Memory allocation leak of 38 bytes at 0x06E74F10 for a StrDup. INTERNAL_ERROR::45 - Memory allocation leak of 16 bytes at 0x06E721A0 for a 'DataFileNameListType' record. INTERNAL_ERROR::45 - Memory allocation leak of 24 bytes at 0x06E74E08 for a 'AddressSpaceLinkType' record. INTERNAL_ERROR::45 - Memory allocation leak of 96 bytes at 0x06F41FD0 for 'void *' data.
  24. Xilinx ise

    Hi Baggey, As far as I know. Xilinx EULA (End User License Agreement) forbids us from shipping the software, either in physical medium or as a download. That is the main reason you have to download it from Xilinx directly. This is far from optimal, we know, but, aside from something I believe Jack is working on (can you confirm @Jack Gassett?, the only way to get the software. Best, Alvie
  25. Unknown Papilio Board

    I had the same error with a new Papilio Duo on Windows 10, trying to load the Papilio_DUO_Quickstart Programming to SPI Flash Using devlist.txt Invalid chain position 0, position must be less than 0 (but not less than 0). Unknown Papilio Board USB transactions: Write 2 read 1 retries 0 Using devlist.txt Invalid chain position 0, position must be less than 0 (but not less than 0). IOException: Cannot open file I found the problem to be an incomplete load of the Xilinx Webpack. At the end of installation, it displays a popup Installation Complete---but it actually is not complete. You have to wait until you get a FINISHED button before pressing on. After completing a reload, the quickstart program worked as advertised.
  26. Xilinx ise

    xilinx ise. What a whopper of a file and a nightmare to get hold off? Im on the second download as origonal thinks its a 1.8Tbyte file!? If its free software and this large and crucial to papillio. Why wasn't it put on a disc and shipped with it? Ive been waiting a long time to get a PRO and when i saw the availability i treated myself for christmas! Just getting bogged down with getting it going.
  27. I cant figure out how to breakout the video signals from the vga adapter symbol/busline to be able to connect them to papilio pro pins. I dont have a megawing, but proto'd a board using the resistor ladder as done on the megawing boards. I want to use the Ch/Cl pins(C1-14) on the papilio pro so I can leave the A and B side open for my comms and switches. 4red,4green,4blue, Horiz and Vert synchs. Is there a tutiorial someone can point me to for this or some advise? Thanks. I'm adding a pic of my board to the post, I made it from the resistor ladder schematic shown on arcade megawing page.
  28. RetroArch running on FPGA.

    Or look at Terasic DE10-Nano which uses large Hybrid-FPGA and very cheap
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