Multicore Architecture Design with Papilio Pro

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I would like to design a multicore architecture using three MicroBlaze softcore(s) which are connected together using FIFO channels and also connected to the shared memory (DDR-RAM) as presented in the attachment.

My question is if I can design the same architecture using Papilio as I've designed it on Genesys Virtex 5 using Xilinx EDK. If yes, which Papilio board should I buy?



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Don't think it would fit any of the Papilio boards. Perhaps the big Pipistrello, have a chat with Magnus ( @mkarlsson ), he should know better than I do (and he uses Microblaze often).


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