bnusbick

Communication over wishbone

12 posts in this topic

Jack,

I ran through the  Papilio DUO – AVR to ZPUino Communication over Wishbone example and it worked fine.  However, it is not apparent to me how to access these same registers using vhdl.  Could you show the changes that would be necessary for vhdl code to increment the register instead of the AVR, in which case the ZPUino code would will still see the register being incremented even if the AVR code was not running.

Regards,

Blake

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Hello Blake,

Unfortunately I won't get much time to put together an example until next weekend so I will try to talk you through what you need to do.

If you look at the image below (from the tutorial) you will see that the Wishbone_to_Registers_x10 symbol exposes the pads for 10 different registers. So anything you connect to them will be readable from your C code on the AVR. In the example below the input is connected to the output, this just means that the registers echo whatever to put in from the C code on the AVR. For your application you will want to remove those wires connecting the inputs to the outputs. Then experiment with connecting VCC and then GND to the register0_in and then verifying that you read back a zero or one from your C code. You can also wire the register0_out to an I/O marker (connected to a physical pin on the Papilio Board) and then verify that you can write to register0 in your code and see the physical pin has the corresponding change. You could then find the example that shows how to make a counter in the schematic editor and implement it and then connect the counters output into the register0_in. 

Connect_Wishbone_Registers_10.png

One important thing that I just noticed is that each register is 32 bits so it is not as simple as just connecting register0_in to an I/O marker or VCC or GND. You will need to connect those single signals to register0_in(0) or register0_out(0) and read the first bit of the 32 bit wide register. You will want to use a bus tap to accomplish that. There is a tutorial here.

Once you get comfortable with doing this from the schematic editor then move on to VHDL. You will want to make a VHDL module that outputs your counter as a port at its top level. Start with making a module that just outputs a 0 or 1 from a port at the top level. After you have created the VHDL module (as a file included in your project) then right click on that file in your file hierarchy list on the left side of ISE and there should be an option to turn the VHDL file into a symbol. Once you successfully run the command to generate a symbol from your VHDL file you should then be able to find it in the symbol navigator and add it to your schematic. Then you connect it to the pads of the Wishbone_to_Registers_x10 symbol.

Hope this gets you rolling in the right direction.

Jack.

 

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Hi Jack,

When I connect wishbone register 1 (0:0) to vcc and then try to synthesize it, it complains with the following errors.

 

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.xst" -ofn "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.syr"
Reading design: Papilio_DUO_LX9.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpu_config.vhd" into library work
Parsing package <zpu_config>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpupkg.vhd" into library work
Parsing package <zpupkg>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuino_config.vhd" into library work
Parsing package <zpuino_config>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuinopkg.vhd" into library work
Parsing package <zpuinopkg>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/sram_ctrl8.vhd" into library DesignLab
Parsing entity <sram_ctrl8>.
Parsing architecture <behave> of entity <sram_ctrl8>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/pad.vhd" into library DesignLab
Parsing package <pad>.
Parsing entity <isync>.
Parsing architecture <behave> of entity <isync>.
Parsing entity <iopad>.
Parsing architecture <behave> of entity <iopad>.
Parsing entity <ipad>.
Parsing architecture <behave> of entity <ipad>.
Parsing entity <opad>.
Parsing architecture <behave> of entity <opad>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/Wishbone_to_Registers_x10.vhd" into library DesignLab
Parsing entity <Wishbone_to_Registers_x10>.
Parsing architecture <rtl> of entity <wishbone_to_registers_x10>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_DUO_V2.vhd" into library DesignLab
Parsing entity <ZPUino_Papilio_DUO_V2>.
Parsing architecture <behave> of entity <zpuino_papilio_duo_v2>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_GPIO.vhd" into library DesignLab
Parsing entity <Wing_GPIO>.
Parsing architecture <Behavioral> of entity <wing_gpio>.
Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_DUO_Wing_Pinout.vhd" into library DesignLab
Parsing entity <Papilio_DUO_Wing_Pinout>.
Parsing architecture <BEHAVIORAL> of entity <papilio_duo_wing_pinout>.
Parsing VHDL file "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" into library work
Parsing entity <Papilio_DUO_LX9>.
Parsing architecture <BEHAVIORAL> of entity <papilio_duo_lx9>.
ERROR:HDLCompiler:806 - "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 537: Syntax error near "=>".
ERROR:HDLCompiler:854 - "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 86: Unit <behavioral> ignored due to previous errors.
VHDL file /home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf ignored due to errors
-->


Total memory usage is 111596 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)


Process "Synthesize - XST" failed
WARNING:ProjectMgmt - File /home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.stx is missing.

 

Could you tell me what I am doing wrong?

I have attached the changed .sch file and generated .vhf file.

Regards,

Blake

 

Papilio_DUO_LX9.sch

Papilio_DUO_LX9.vhf

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Jack,

The problem appears to be with creating the bus tap.  When it didn't like it, the single bit of the bus tap was connected to vcc.  When it did like it, the single bit of the bus tap was connected to one of the 32 bits of the wishbone register (i.e. both sides of the bus tap were connected to the same XLNX_ symbol).

Another problem I had was that whenever I would save the schematic after changes, ISE would hang (I am using Lubuntu 14.04) and I had to end the process to gain control again.  It does seem the changes were getting saved though, since when I edited the circuit again, I saw the changes.  However, when I went into ISE directly and edited the circuit directly instead of pressing the edit circuit button in DesignLab 1.07 to edit the circuit, it would save my changes without hanging ISE.

I will keep trying to carry out the experiments you suggested.

Regards,

Blake

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Jack,

I don't understand what connecting the wishbone reg0 inputs to the wishbone reg 0 outputs does.  Even when I disconnect reg 0 input from reg 0 output and apply vcc to one of the bits of the reg 0 input, I see it on that bit on the reg 0 output, so they still must be connected in some way.  Could you explain the difference between the two scenarios?

Regards,

Blake

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Hi Jack,

Could you provide a link to the example of creating a counter in the schematic editor?  I don't see it on your learn site.

Regards,

Blake

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Jack,

When I try to add clk to the attached schematic, it complains with the following:

Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=P94) which requires the combination of the symbols listed
   below to be packed into a single IOB component.

I don't see clk listed in the .pcf file that contains the net list, but somehow it knows that it is P94. 

I do see the following in the .pcf file:

        COMP "ext_pins_in<0>" LOCATE = SITE "P94" LEVEL 1;

but when I tried to name the i/o connector ext_pins_in(0), it didn't like that either.

So, what do I need to do to make the attached schematic output a 30  Hz signal on I/O pin Arduino8?

Regards,

Blake

Papilio_DUO_LX9.sch

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Hello Blake,

Sorry for the slow response, I've been on a job which was running late every night last week and then Fathers day weekend this weekend... I should get some time this wednesday to take a look at this and help out.

Jack.

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Hi Jack,

I have been trying out the steps you suggested, and I got them all to work.   Thanks for the suggestions.

Besides the original question of how to write to a wishbone register in VHDL, I have the remaining questions from my previous emails.

1) I could get clock input to the counter circuits by connecting clk_osc_32MHz to clk_32MHz (see the attached Papilio_DUO_LX9save5.sch).  However, if I just created an IOB of clk_osc_32_MHz and connected it to clk_32_MHz, the wishbone register reads always read 0.  Shouldn't these be equivalent? Also, when I tried to connect on IOB of clk to clk_32_MHz, it got the following error when I tried to generate the bit file (see the attached Papilio_DUO_LX9.sch).

ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=P94) which requires the combination of the symbols listed
   below to be packed into a single IOB component.

(I got the same error whether I made clk an input or output.)

2) What  does connecting a wishbone register's input to its output do? When I don't connect the wishbone's register to its output, I still see the counter output that is connected  to the wishbone register input when I read the wishbone register output.

I  also encountered the following annoyances. Whenever I opened ISE using edit circuit from DesignLab, ISE hung when I saved the .sch file after making changes.  It did save the file though, so I could just end the ISE process and edit the circuit again to see my changes.  To get around this annoyance, I would run ISE outside of Designlab, and just use Designlab to load the circuit.  I also had to change the name of the generated bit file from Papilio_DUO_LX9.bit to papilio_duo_lx9.bit, since Designlab load circuit would only recognize it if it was in all lowercase.

Regards,

Blake

Papilio_DUO_LX9save5_works.sch

bfn_counter.vhd

Papilio_DUO_LX9.sch

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Jack,

When do you think you will get time to answer my above questions?

In the meantime, I found the following:

https://ceworkbench.wordpress.com/2015/10/03/adapting-wishbone-cores-for-use-with-the-papilio-and-designlab/

and tried to implement it.  When I tried to perform the following step:

         "To start, open DesignLab and select Papilio : New DesignLab Library – Wishbone VHDL to create the project. Change the name to BasicWishbone and click OK to save it."

ISE hung.  Can you give me a hint as to how I can stop ISE hanging when I do this?

I then opened ISE alone and saw that it created BasicWishbone.  I continued  to follow all the steps, but when it came time to create the schematic symbol, it had the following errors:

ERROR:HDLParsers:3317 -
   "/home/bn/DesignLab/libraries/BasicWishbone/Chip_Designer/../BasicWishbone.vhd" Line 24.  Library DesignLab cannot be found.
ERROR:HDLParsers:3014 -
   "/home/bn/DesignLab/libraries/BasicWishbone/Chip_Designer/../BasicWishbone.vhd" Line 25. Library unit DesignLab is not available in library work.

due to the following statements in BasicWishbone.vhd:

     library DesignLab;
     use DesignLab.ALL;

Can you tell me what I need to do so it can find the library DesignLab?  Do I need to copy it somewhere, or is the result of New DesignLab call to ISE hanging and something not getting copied correctly?

Regards,

Blake

 

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Jack,

I just installed DesignLab 1.08 on a Windows 7 computer to see if I could avoid ISE hanging when I launch it from DesignLab.  The installation of DesignLab and Xilinx ISE went fine, but when I tried to edit the AVR_to_ZPUino_Communications circuit, I got a popup that stated "Sorry, no Xilinx project file found in the libraries or project directory".  I get the same message when I try to edit any circuit.

How do I go about fixing this problem?

Regards,

Blake

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