kyson

Interfacing memory to papilio fpga board

2 posts in this topic

I now have a papilio fpga board and although I've for now abandoned my previous project for now I would like to interface this to an external static ram as a learning exercise.

So I was thinking of getting a static memory chip something like this one and making a small breakout board pcb for it (probably using seeed studio or similar to get it made), bringing out the pins to a female header row. I can then connect to my papilio using simple wires.

Now, assuming my soldering is up to actually making such a board, is there any reason why such a board wouldn't work? I realise that having 30 or so wires connecting the two boards probably limits the speed I'd be able to use the memory at, but was wondering if it would work at all and if so what access speed I'd likely be able to get working?

The purpose of this is mostly because I want to try it even if there are better solutions I could just buy... and to give me the hardware I need to understand making memory access controller in verilog. I don't expect this to be fast enough to generate video signals from but wondered what kind of speed I might expect to work with such an arrangement?

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No, there is no reason why a board like that would not work.  I would keep the wires as short as possible though.  One option is to make the layout to match the papilio wing headers and populate the board with pin headers to minimize the signal length.

The memory you linked to has a 12ns access time and you should be able to do reads and writes at 25 - 40 MHz.  A quick rule of thumb is to add 5ns address output delay and 5 ns data input delay to the 12ns access time = 22ns access cycle time.

You should be able to use this memory to generate video signals at 8 bits/pixel, 640x480.  The problem is that if you want to dynamically update the video image then you would need bandwidth for both video readout access and video update access.  For 640x480 VGA that typically means the you need 50 MHz pixel access bandwidth (2x 25 MHz video pixel rate).  If this is your goal then you might want to consider a 10nS memory part.

Here is a link to a zip file with a Eagle board layout for a memory board that fits the Papilio headers: http://www.saanlima.com/download/sram_wing1.zip  It implements a 32-bit wide 2MB memory system using two 512Kx16 SRAM chips and an address latch to save pins.  This board has up to 100 MB/s bandwidth using 10nS memory chips and can be used to implement a 16-bit/pixel VGA buffer with read/write access bandwidth.  While this is a bit more than what you plan to do, it might give you some ideas.

Magnus

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