mkarlsson

Mac Plus with SCSI disk support running on LX9

2 posts in this topic

This is a port of the Plus Too code from Big Mess o' Wires to Pepino LX9/1MB. This code base have been dormant for quite some time but the folks at MiST picked it up a while ago and added more features like keyboard and sound support etc. The code supports a virtual SCSI hard drive via the sd-card socket. This is based on the MIST scsi code but the disk interface is quite different - the MIST board have a ARM processor that is handling the sd-card read and write functions and talks to the FPGA via SPI, while in the Pepino implementation the FPGA is directly connected to the sd card using the native 4-bit SD protocol.

The interesting part of this project is that the 128KB ROM data is stored in flash memory after the bit file and is executed directly from the flash chip (the need for this is due to the Pepino LX9 RAM limitation, the MacPlus needs the full 1MB of RAM).  It's possible to do this since the flash chip on Pepino (Micron N25Q128A) can operate in quad-spi mode at up to 108 MHz clock rate.  In quad-spi mode, 4 bits are transferred on each clock instead of 1 bit.  However, due to access time restrictions there needs to be dummy cycles between the cmd/address part and the data transfer part based on the clock frequency used.  The default number of dummy cycles is 10 matching the highest clock rate (108 MHz).  So with the default dummy clock settings a 16-bit word transfer in quad-spi mode will take 2 + 6 + 10 + 4 = 22 clocks, corresponding to 1 byte command, 3 byte address, 10 dummy clocks and 2 byte data. (BTW, there is a possibility to eliminate the command byte by using XIP, eXecute-In-Place mode supported by this chip, but it was not needed in this case). 

In this project the spi bus is clocked at 65 MHz and the Mac 68000 processor is clocked at 8.25MHz.  The 68000 memory access cycle takes 4 clocks for an effective memory access rate of about 2 MHz, which means that there is time for 32 spi clocks for each memory access (65 MHz/2.03125 MHz = 32).  So the 22 clocks needed to read one instruction in quad-spi mode will easily fit in the 32 cycle window.

The full ISE project can be found here: http://www.saanlima.com/download/pepino-v1.1/PlusToo_scsi_LX9.zip

For more info and a MacPlus disk image etc., see this link: http://www.saanlima.com/pepino/index.php?title=Pepino_PlusToo

http://www.saanlima.com/images/128M.JPG

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