hjm142 Posted February 22, 2017 Report Share Posted February 22, 2017 Hello, I have a very simple project programmed into the FPGA and I am monitoring all of the I/O directly through ChipScope. Currently, I am experiencing some issues with implementing a UART. At this point, all I am really doing is monitoring the RX line (pin 101) for any edge triggers. Through the FT Prog tool, I have verified port B is setup as a virtual com port and as an RS232 UART. The com port shows up in device manager as expected. I've disabled chan A, so I am confident that I am picking the correct com port. When I open putty or tera term and try to send some random data over this line, I do not see any activity on chipscope. Chipscope is clocking because I can trigger on other signals. Tomorrow, I will look at the FPGA and USB-to-UART chip (U3) under a microscope and see if I can see any loose pins or solder joints. I will also check the continuity between the sets of pins to rule out trace problems. If I can get my hands on one, I will probe U3 with a scope and verify I have chipscope setup to reflect reality. I may not have access to one this week though... which is the reason for my question: is there anything else that I may be overlooking in initial setup? Jumpers, etc? Appreciate any additional insight. Thanks! Quote Link to comment Share on other sites More sharing options...
hjm142 Posted February 22, 2017 Author Report Share Posted February 22, 2017 This has been resolved. I had placed channel A in opto isolation to use a JTAG connector and channel A appears to be mapped to the RX/TX lines rather than channel B. Seems backwards from the hardware pin-out, but it works. Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted February 22, 2017 Report Share Posted February 22, 2017 Glad to hear you got this working. Jack Quote Link to comment Share on other sites More sharing options...
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