WoWPro71

Where is the reset

8 posts in this topic

hello,

i couldnt  connect the reset button which is pin 38, it said that it doesnt exist. where is it truly placed?

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I believe that's the wrong pin [in reference to a question about the clock input, and pin P55, that has been edited out I think].  The Papilio DUO generic UCF file has the following:

NET CLK      LOC="P94"  | IOSTANDARD=LVTTL;                                     

TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%;

P55 seems to be one of the external pins on the board.
 
Generally finding out what pins map to what, I rely on the published UCF files from this site, and then if there's a confusion I refer to the schematic.  Note that there is more than one set of pin numbers (FPGA, and board) and more than one kind of thing termed "clock" (SPI bus clock signal for example).
 
I don't see the references that identify P55 as clock or P38 as reset.
 
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9 minutes ago, Jaxartes said:

I believe that's the wrong pin.  The Papilio DUO generic UCF file has the following:

NET CLK      LOC="P94"  | IOSTANDARD=LVTTL;                                     

TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%;

P55 seems to be one of the external pins on the board.
 
Generally finding out what pins map to what, I rely on the published UCF files from this site, and then if there's a confusion I refer to the schematic.  Note that there is more than one set of pin numbers (FPGA, and board) and more than one kind of thing termed "clock" (SPI bus clock signal for example).
 
I don't see the references that identify P55 as clock or P38 as reset.
 
 
 

i was mistaken the reset is 37 not 38. i opened someones UCF file and its indeed P94 for the clock. now i only need to find a way to use the reset button that is on the board.

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its saying :

ERROR:MapLib:30 - LOC constraint P37 on ireset is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

i wrote this:

Net "ireset" LOC = "P37"  | IOSTANDARD = LVCMOS33 ;

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The "FPGA reset" pin resets this FPGA itself.  So maybe the Xilinx software doesn't let you use that pin.  There wouldn't be any purpose in using it, since your logic wouldn't be running while the FPGA is being reset.

So you'd need to find an alternative.  Some that come to mind:

  • If you've got a shield board plugged into the Papilio DUO, and that shield board has one or more buttons, you can use one of the buttons as your reset.
  • There's a slide switch on P104.  If you're not using it for anything else, you could use it as a reset.  It's a little inconvenient to use a slide switch for that, because you'd have to move the switch twice (once to reset, and once to stop resetting).
  • It's also possible to write some logic that processes the switch state, so that every movement of the slide switch generates a reset.  It's not trivial but it's fairly simple.  The easiest way for me to describe the logic is to write it in Verilog; here goes:
    module reset_finder(input clk, input slide_switch, output switch_moved);
        reg slide_switch_delayed = 1'd0;
        always @(posedge clk) slide_switch_delayed <= slide_switch;
        assign switch_moved = slide_switch != slide_switch_delayed;
    endmodule

 

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You cannot use the reset pin from a circuit running inside the FPGA, it is only meant as an external reset.

Your options are to build reset functionality into your VHDL code and assign that reset functionality to a button attached to a GPIO pin on the FPGA. This is the most common practice.

Or you can use the Global Reset option of the startup_spartan6 primitive as detailed in this forum thread:

 

Jack.

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