james1095

FPGA vector games

19 posts in this topic

I just wanted to show off my latest FPGA project, this is not currently Papilio based but I'm contemplating doing a megawing for the Papilio One/Pro if there is enough interest, I don't want to manufacture it but I would open source the design. For the time being this is based on the little Altera Cyclone II boards that can be had for about $13, cheap enough to integrate into projects. I designed a daughterboard that plugs onto these and holds a triple DAC, op-amps with gain and offset adjustments for the X and Y deflection, a DC-DC converter to provide the +/-15V rails for the amps, an audio amplifier with volume control and I tossed in a I2C EEPROM with hopes of using it to emulate the EAROM that stores the high scores in Asteroids Deluxe. Initially I tried using delta-sigma DACs for the deflection as Spritesmods did with his Black Widow project but I was not happy with the result. Then I got the idea to use a VGA DAC since it's a high quality high speed 10 bit triple DAC and there was one on my DE2 dev board that I used for prototyping. It worked perfectly so I carried it over to this design. The monitor is based on a cheap 5" B&W CRT TV with the vertical winding of the deflection yoke rewound and a custom electronics, the initial deflection board was designed by Fred Kono a number of years ago but I'm working on a cleaner and more integrated solution. I've also tested this FPGA board with a G05 and a 19K6101 vector monitor in my fullsized cabinets and it drives them fine.

 

As it stands, I've got Asteroids Deluxe working perfectly using code originally from fpgaarcade.com modified to eliminate the rasterizer and ported to my hardware. As of yesterday I also have the original Asteroids working except I have not modeled the analog circuits for many of the sounds which Deluxe replaced with a POKEY chip. If anyone is interested in helping out with this project there are a few items on the to-do list that I could use a hand with, in the process I'd be happy to post the code I have and provide all of the details for anyone who wants to replicate this to do so. Eventually my plan is to build a few miniature arcade cabinets replicating the original classic games in small desktop form.

 

To do:

- Implement missing sound effects in Asteroids, all of the control logic is there and working, still need the thump-thump, ship and saucer firing sound and saucer warble.

- Implement EAROM emulation, I'm not entirely certain how feasible this is but I included an EEPROM because there was space. It's trivial to use a block RAM in place of the EAROM but that needs to be backed up to and restored from the serial EEPROM.

- Get Lunar Lander working on the platform, I made an initial attempt and was not successful, I plan to give it another go. I've brought out the I2C bus on my board with thoughts of using a I2C ADC for the thrust input.

- Implement Omega Race hardware, this is a much larger task since it's a completely different hardware platform. It uses the same 10 bit DACs as the Atari games and the hardware is of similar complexity.

 

 

One last thing worth mentioning, these little CRT TVs are currently fairly easy to find but they are going away fast. They are essentially useless to most people since the death of analog TV but they are perfect for projects like this, a real CRT is the only way games like this look right at all, if you come across these things pick them up while you can because nobody is making CRTs anymore and they are disappearing fast.

asteroids.JPG

Asteroids Deluxe.JPG

Asteroids Deluxe closeup.jpg

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This is really exciting and I applaud your work. I would love to have Asteroids running on an fpga so I will be following this. Great job!

Sent from my VS985 4G using Tapatalk

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Well here's where I am with this so far, I'm posting these in case I get hit by a bus or something, one of my pet peeves is when people show off cool projects but then never release the code, so here's the code. Currently this is set up for an Altera FPGA but it was originally written for Xilinx and I do intend to port it back to the Papilio, doing so is relatively easy. These are set up to work with the program ROMs in an external parallel EEPROM because the little EP2C5T155C8 I'm using lacks sufficient block RAM to hold all the ROMs internally but the FPGA on the Papilio boards is large enough that this is not needed.

 

Anyway here's the state of things:

Asteroids Deluxe - Fully working, no high score save yet but that was never implemented by MikeJ who originally released this on fpgaarcade.com

Asteroids - Works but several of the sounds are missing which really detracts from the game. If someone wants to work on modeling the missing sound circuits that would be cool.

Lunar Lander - This is not working at all yet and I'm banging my head against the wall trying to determine why. The hardware is very, very similar to that of Asteroids, more ROM, less RAM, one of the input banks is done differently, it also has an analog input for the thrust control but that shouldn't be necessary for the attract mode to run. I could really use a bit of help getting this to run at all at which point I'll work on the details. Currently I've got the watchdog disabled because otherwise the reset keeps pulsing. Trying to figure this out has distracted me from finalizing the hardware revisions and polishing up the other two games. I printed out the schematics, highlighted all the changes I could find and then methodically implemented them in the code but it's possible I missed something somewhere.

Asteroids Deluxe.zip

Asteroids.zip

Lunar Lander.zip

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2 hours ago, james1095 said:

 

Lunar Lander - This is not working at all yet and I'm banging my head against the wall trying to determine why. The hardware is very, very similar to that of Asteroids, more ROM, less RAM, one of the input banks is done differently, it also has an analog input for the thrust control but that shouldn't be necessary for the attract mode to run. I could really use a bit of help getting this to run at all at which point I'll work on the details. Currently I've got the watchdog disabled because otherwise the reset keeps pulsing. Trying to figure this out has distracted me from finalizing the hardware revisions and polishing up the other two games. I printed out the schematics, highlighted all the changes I could find and then methodically implemented them in the code but it's possible I missed something somewhere.

 

 

i dont do any vhl, but did you try changing the state of the halt bit ?

i only mention it because mame shows some stuff as active high // active low in the source that doesnt match between LL and Asteroids Deluxe

asteroids deluxe has halt as active low on bit 3 
while Lunar Lander has halt as active high on bit 0

its probably worth checking slam (tilt) state too since the same low/high reversal exists between the two.

sorry cant be of more help.  really need to get back into vhdl for dummies :)

 

 

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I found Free Range VHDL to be an excellent book, and it's free in digital form too.

 

 

Anyway back to the Lunar Lander issue, I *think* I accounted for the differences you mention. Attached are snippets of the input 0 buffers for both Asteroids and Lunar Lander. Note that Asteroids uses a 74LS251 which is a selector/multiplexer with an inverted output read on D7. Lunar Lander on the other hand uses a 74LS367 tristate buffer which is non-inverting and read on D7, D6, D2, D1 and D0, both are active when SINP0 goes low.

 

Now for the code, here's a snippet from Asteroids:

    -- self test, slam, diag step, fire, hyper
    control_ip0_l <= "11111";
    control_ip0_l(4) <= SELF_TEST_SWITCH_L;
     control_ip0_l(3) <= '1';             -- slam
     control_ip0_l(2) <= '1';             -- diag step
    control_ip0_l(1) <= BUTTON(4);     -- fire
    control_ip0_l(0) <= BUTTON(5);     -- shield
    test_l           <= SELF_TEST_SWITCH_L;


 p_input_sel : process(c_addr, dips_p6_l, control_ip0_l, control_ip1_l, clk_3k, halt)
  begin
    control_ip0_sel <= '0';
    case c_addr(2 downto 0) is
      when "000" => control_ip0_sel <= '1';
      when "001" => control_ip0_sel <= not clk_3k;
      when "010" => control_ip0_sel <= not halt;
      when "011" => control_ip0_sel <= not control_ip0_l(0);
      when "100" => control_ip0_sel <= not control_ip0_l(1);
      when "101" => control_ip0_sel <= not control_ip0_l(2);
      when "110" => control_ip0_sel <= not control_ip0_l(3);
      when "111" => control_ip0_sel <= not control_ip0_l(4);
      when others => null;
    end case;
    
    
    
    
    p_cpu_data_mux : process(c_addr, ram_dout, rom_dout, vg_dout, zpage_l, pmem_l, vmem_l,
                           sinp0_l, control_ip0_sel, sinp1_l, control_ip1_sel,
                           dpts_l, dips_ip_sel)
  begin
    c_din <= (others => '0');
    if (sinp0_l = '0') then
      c_din <= control_ip0_sel & "1111111";
    elsif (sinp1_l = '0') then
      c_din <= control_ip1_sel & "1111111";
    elsif (dpts_l = '0') then
      c_din <= "111111" & dips_ip_sel;
    elsif (zpage_l = '0') then
      c_din <= ram_dout;
    elsif (pmem_l = '0') then
      c_din <= rom_dout;
    elsif (vmem_l = '0') then
      c_din <= vg_dout;
    end if;
  end process;

 

Note that each of the signals in the first section is inverted, accounting for the inverted output of the selector/multiplexer.

 

Now looking at a snippet (with some irrelevant bits removed for clarity) from Lunar Lander:

 

 p_input_registers : process
  begin
    wait until rising_edge(CLK_6);

    -- diag step, 3khz, slam, self test, halt
    control_ip0_l <= "11111";
    control_ip0_l(4) <= '1';            -- diag step
    control_ip0_l(3) <= clk_3K;      -- 3 khz
    control_ip0_l(2) <= SELF_TEST_SWITCH_L;
    control_ip0_l(1) <= '1';             -- slam    
    control_ip0_l(0) <= halt;     

  end process;
 
 
 
 
   p_cpu_data_mux : process(c_addr, ram_dout, rom_dout, vg_dout, zpage_l, pmem_l, vmem_l,
                           sinp0_l, control_ip0_l, sinp1_l, control_ip1_sel,
                           dpts_l, potin_l, potval, dips_ip_sel)
  begin
    c_din <= (others => '0');
    if (sinp0_l = '0') then
      c_din <= control_ip0_l(4 downto 3) & "111" & control_ip0_l(1) & control_ip0_l(2) & control_ip0_l(0);
    elsif (sinp1_l = '0') then
      c_din <= control_ip1_sel & "1111111";
    elsif (dpts_l = '0') then
      c_din <= "111111" & dips_ip_sel;
     elsif (potin_l = '0') then
        c_din <= potval;
    elsif (zpage_l = '0') then
      c_din <= ram_dout;
    elsif (pmem_l = '0') then
      c_din <= rom_dout;
    elsif (vmem_l = '0') then
      c_din <= vg_dout;
    end if;
  end process;

 

Note that in this case there is no intermediate step so I'm not inverting those signals, and rather than the signals being read one at a time onto bit 7 of the data bus, they are all fed simutaneously to the CPU data in when sinP0_l is low.

Asteroids IP0.jpg

Lunar Lander IP0.jpg

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thanks for the explanation.

do you have a link to the rest of the schematics ? or can you attach them here?

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I've ported the Lunar Lander code over to the Papilio in case someone here is able to take a crack at getting it working. I'm out of town and didn't bring my Papilio boards with me so I don't know how this behaves but it builds fine, just grab the MAME ROM and extract the files into the rom folder and run the build_roms batch script and it should build no problem, currently set up for the P1-500k. I didn't have enough IO pins to hook up the mission indicator lamps but I think enough can be freed up by disconnecting unused button inputs, otherwise a shift register could be used as IO expansion. Without a DAC it won't drive a monitor but if the X and Y outputs are active and the watchdog isn't barking then that's a good indicator that things are working.

Lunar Lander Pap1.zip

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thanks for the schematic links.

wish i could help but only way would be to use the scopes @ work and i am sure that work would not appreciate it at all :)

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The simulator built into ISE is probably the most effective approach, I'm still not particularly skilled at using it though. There are a few pretty talented FPGA developers floating around here, hopefully one of them will take a peek through the code.

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This is driving me nuts! I spent several hours looking through the output in ISim and I still haven't figured this out. I can see it start reading from the program ROMs and it runs through a loop initializing all locations in the CPU RAM and everything looks ok there, but then somewhere along the line it ends up out in the weeds stuck in a loop writing to the same location of RAM and eventually the watchdog resets it. I played around with the vector generator in isolation and I can read and write the RAM and read the ROM in the expected memory locations and the data it returns matches the ROM images, at least the random addresses I checked. It doesn't appear to even get to a place where it tries reading the inputs (which include Halt and such) so I don't think the problem is in that area. It's just weird because Asteroids and Deluxe work fine, I may have to try those in ISim and see what that does.

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Hey James,

When I was debugging the AVR8 and getting it to work with Arduino IDE in the beginning one thing that I did that got me past a hard problem like you are describing is to run an AVR simulator and compare everything step by step. So maybe Mame or something can be used to look at the internals and then step through until you get to the part that is looping and compare it to what is supposed to be happening?

Jack.

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That's probably a reasonable way to go about it, I'm not sure I have the skills and mental energy to try right now though, I've been beating my head against a wall for weeks now trying to get this to work and I need to force myself to take a break and finish up the hardware side. If I have a complete monitor design that others can duplicate, maybe others will want to build these too and then a Papilio vector megawing could make sense. I'm not trying to compete with Gadget Factory in any way with this project, I'd love to see others jump in and take it further. FPGA based retro arcade development seems to have seriously stalled since the initial batch of games released quite a few years ago.

 

In the meantime I'm hoping I can convince someone else to take a crack at this, it's possible that the problem will be obvious to a second set of eyes. Unfortunately outside of this forum I've found very little in the way of hobby FPGA discussion, I've tried and failed to get any of the other techie people I know interested enough to get over the very steep initial learning curve.

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did you check with mame debugger where things start to go wrong ?

Is it possible one of the input signals is accidentally active when the cpu expects to read rom ?

(didn't check the code yet :)

 

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I don't know how to use the MAME debugger, that isn't something I've ever done.

 

I don't think I ever saw the input latch signals assert during the simulation runs I tried, it's relatively easy to load it up in Isim and do a run though.

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If you start mame with the '-debug' option you should start up with a really powerful debugger. (with builtin help )

 

isim seems to want all signals preset or it doesn't do anything meaningful (or maybe i was not patient enough)... it really isn't a 5 minute job to rig up a tb from the sources.

 

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Interesting, I'll have to give that a go and see what I can do.

 

Yes it does need signals to be preset, I can post my test bench files when I'm home, they're simple but it's not as simple when you haven't been dealing with the code. I had to figure out a few things but I was able to get Isim to work on it. I had to make sure I set Reset_l high, and I think I had to add a default value for the clock divider signal.

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i basically gave up after 30 minutes ... an army of new 'U' signals seemed to pop each and every time i thought i'd got them all.. sorry.

 

 

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That's fine, thanks for giving it a go. I'll take a look over the weekend and upload a ready to go configuration.

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