Larry McGovern

Logic Analyzer bug on Papilio One?

9 posts in this topic

I'm seeing some strange behavior with the Papilio One Logic Analyzer any time I select a sample size greater than 6 kB.  It is easiest to demonstrate with an example.

I have a test signal coming in on Pin 0.  I am writing the sentence "The quick brown fox jumped over the lazy dog" over a serial port at 115200 baud, and repeating the sentence every 30 msec.  The sentence itself takes 4 msec to write. 

The first image below shows a 1 MHz, 6 kB capture enabling channel group 0.  This should cover 6 msec of data, and that is what I see on the logic analyzer.  The UART analyzer shows the correct sentence coming across.

The second image shows a 50 kHz capture, with 120 msec of data.  This shows the sentence is repeated every 30 msec.

The third image shows a 2 MHz, 12 kB capture enabling channel group 0.  It should look exactly the same as the first image, but it doesn't.  Instead, it shows a 1.5 msec word, 1.5 msec gap, and another 1.5 msec word.  The two words read "er the lazy dog     er the lazy dog". 

The fourth image shows a 5 MHz, 24 kB capture.  Again, it should look like image 1 but it doesn't.  Instead, we see the last 0.75 msec of the sentence, repeated 4 times.  It essentially says "** dog" four times, where ** are garbage characters.

That was all with only channel group 1 enabled.  When I enable all four channel groups, and do a 1 MHz, 6 kB capture, I am told I will only receive 1.5 msec of data, but instead I receive 6 msec of data!  When I try to capture 12 kB or 24 kB of data, it complains "Sample count too large for chosen channel groups!" 

So... Is this a known bug, or something new?  I installed the bitfile using the "OLS" button on DesignLab 1.0.7.  I have been extra careful to ensure I have selected the Papilio One 250K on both DesignLab and OLS.  I've even uninstalled and reinstalled DesignLab.  I also have a Papilio Duo, and the logic analyzer works for me with that board. 

Any ideas?  Anything I should try?

Capture1.JPG

Capture2.JPG

Capture3.JPG

Capture4.JPG

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Hello Larry,

Ok, looks like you are using a 250K? If I remember correctly I had found a bug with the bit file for the 500K and 250K and generated a new bit file. Let me retrace my steps to verify that is correct.

Oh, and just to verify, are you saying that the same test you did above works with the Papilio DUO?

Jack.

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Ok, I'm working on generating a new bit file to test with... The bit files that were included with DesignLab for the 250K and 500K had a weird fuse set on them that created some instability that showed up when trying to load the Logic Analzyer bit file more then once. I thought that was the only case that was a problem, but maybe it is more then that. I'll work on new bit files and post when they are done. 

Jack.

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Hi Jack, no dice :( 

The 250k bit file has exactly the same behavior on channels 16-31.  I could not get channels 0-15 to work at all.  I went back to the bit file that comes with DesignLab 1.0.7.  (By the way, I did try the 500k file as well, but couldn't collect any data with that one.)

Incidentally, my "test" was super simple.  I just loaded the following sketch to an arduino board, and connected pin Tx and GND to the Papilio.  Just in case you wished to replicate these results.

void setup() {
  Serial.begin(115200);
}

void loop() {
  Serial.println("The quick brown fox jumped over the lazy dog");
  delay(30);
}

 

 

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And missed your question about the Duo earlier.  Yes, I have verified it in the past, but not with this exact test.  I was using the logic analyzer with it a month or two ago, with no problems.  I have it wrapped up in another project at the moment, but could pull it out if there is anything you want me to try on it. 

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On 11/11/2016 at 8:32 PM, Larry McGovern said:

That was all with only channel group 1 enabled.  When I enable all four channel groups, and do a 1 MHz, 6 kB capture, I am told I will only receive 1.5 msec of data, but instead I receive 6 msec of data!  When I try to capture 12 kB or 24 kB of data, it complains "Sample count too large for chosen channel groups!"

The problem above is related to bugs in JaWi's SUMP client, not the FPGA board.  When the pulldown menu says 6 kB capture it really means 6 kS, i.e. it's the number of samples not the number of bytes.  But then in the time calculation he incorrectly scales the resulting time by the number of channel groups.  6 kS at say 1 MS/s will always take the same time (in this case about 6 msec) independent of how many channel groups are enabled.  If you try to select 12 kB or 24 kB samples (really 12 kS or 24 kS) with all four channel groups enabled then the memory is not enough so the error message is correct.

As an alternative to Jack's Sump Logic Analyzer bit files for Papilio One 250k/500k you could try one of the bit files here: http://www.saanlima.com/download/Papilio_One/ , they are generated from the current Open Bench Logic Sniffer Verilog source files.

Cheers, Magnus

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