virtualrobotix

Add new Wishbone module to Papilio Duo Zpuino app some doubt help me to understand please :)

8 posts in this topic

I found an interesting project it is advanced implementation in OpenCores of FM Trasmitter that accept in input an audio streaming and add it to FM RF modulation .

The project is this : 

FM Transmitter Hack

http://opencores.org/project,wbfmtx 

This is the link to the code  : 

http://opencores.org/websvn,filedetails?repname=wbfmtx&path=%2Fwbfmtx%2Ftrunk%2Frtl%2Fwbfmtxhack.v

What i understand is that module is in verilog and not in vhdl is possible to develop a project with mixed language ? This is my first question . 

The other question is about wishbone bus , i read the implementation in ZPUINO http://www.xess.com/blog/extending-the-zpuino/

I follow this tutorial  

http://www.xess.com/blog/extending-the-zpuino/

it's clear but i have some problem to understand how the wishbone bus describe in ZPuino is compatibile with the module that i would add to my project. 

--
-- IO SLOT 9
--

slot9: zpuino_empty_device
port map (
  wb_clk_i  => wb_clk_i,          -- Clock to peripheral.
  wb_rst_i  => wb_rst_i,          -- Reset to peripheral.
  wb_dat_o  => slot_read(9),      -- Data from peripheral.
  wb_dat_i  => slot_write(9),     -- Data to peripheral.
  wb_adr_i  => slot_address(9),   -- Address to peripheral.
  wb_we_i   => slot_we(9),        -- Write-enable to peripheral.
  wb_cyc_i  => slot_cyc(9),       -- Cycle handshake to peripheral.
  wb_stb_i  => slot_stb(9),       -- Chip-select to peripheral.
  wb_ack_o  => slot_ack(9),       -- handshake acknowledge from peripheral.
  wb_inta_o => slot_interrupt(9), -- Interrupt from peripheral.
  id        => slot_ids(9)        -- Peripheral ID (not part of Wishbone).
);

And the interface inside the module , but my opinion is it is different or i don't understand how interface the bus  ? 

I have experience in schematics design of micro controller and memory bus so i understand the bus concept but i don't understand how the ZPuino bus could be compatible with wbfmtxhack this is the whisbone descriprtion : 

Quote

module	wbfmtxhack(i_clk, 
		// Wishbone interface
		i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
			o_wb_ack, o_wb_stall, o_wb_data,
		o_tx, o_int);
	parameter	DEFAULT_RELOAD = 16'd1814; // 44.1kHz at a 80MHz clock
	input	i_clk;
	input	i_wb_cyc, i_wb_stb, i_wb_we;
	input		i_wb_addr;
	input	[31:0]	i_wb_data;
	output	reg		o_wb_ack;
	output	wire		o_wb_stall;
	output	reg	[31:0]	o_wb_data;
	output	wire		o_tx;
	output	reg		o_int;
 

It's different respect the bus in ZPuino 

i_wb_cyc,

i_wb_stb,

i_wb_we,

i_wb_addr,

i_wb_data,

o_wb_ack,

o_wb_stall,

o_wb_data,

What i don't understand ? I'm a very good background in C / C++ but is the first time that i try to develop a complex code on FPGA . 

Someone can help me please  to understand please :)

Best

Roberto 

 

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Re mixing Verilog and VHDL: Yes, it can be done.  I think it's not very difficult.

Re Wishbone bus:  It looks like both sides are using the Wishbone bus.  The signal names are different, a few signals are missing from one or the other, and it's possible there are semantic differences between signals with similar names.  I'd recommend looking at the wbfmtx page at OpenCores for some documentation of its Wishbone interface.  Like maybe this one here: http://opencores.org/websvn,filedetails?repname=wbfmtx&path=%2Fwbfmtx%2Ftrunk%2Fdoc%2Fspec.pdf.  (E.g. it says o_wb_stall is always set to zero)  Also the Wishbone bus specification is worth looking at.  That can be found at OpenCores too.

Overall: I recommend trying a less ambitious project.  Interfacing two complex cores together is tricky.  Writing your own Wishbone core and interfacing to that, might be a good "warm up" exercise.  When I was in a similar situation, I ended up writing a small Wishbone "timer" device.  The advantage of a timer is it has easy to understand and investigate behavior, and it has no external interfacing other than the Wishbone bus.

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Thanks Jaxartes for your  reply .

I recived a mail from developer of code and he told me that not need use all the signal in the bus but only someone now i try to understand better who are need and what i don't need to try to integrate in my papilo board sure could be possible to implement different tutorial or modify code already available for understand better how work the bus. 

Do you have a link to some tutorial ? What i don't need exactly is how is connected the bus to module in the code ... so if i think to the schematics is clear how connect some pin to other ... but in the bus is not wire connected to other divice but buy a bus so i don't exactly understand how connect specific pin to other specific pin in the module that is not clear to me but try to learn myself or with some support for the community ;)

But when the bus is connected in ZPuino how i see that bus by a mechanism like ioclt or memory access to a specific memory location is correct ? 

bye and thanks a lot 

Roberto 

 

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Thank you Jack for your support :) And congratulation for your great Job on FPGA . 

I discover a new world and learn a lot on FPGA by your great opensource project. 

I'm co founder of another great opensource project. Ardupilot.org ... I'm evaluate how we can integrate this 2 worlds. I think could be possible or with softcore cpu , sdr or camera .... Mumble Mumble Mumble :)

What do you think about ? More simple task could be port ardupilot on softcore like avr 8 or zpuino . 

Best

Roberto 

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Phew, sorry for the slow reply to this really interesting post! I was traveling home after vacation the last couple of days.

I think that would be absolutely amazing to integrate our two worlds. I've looked at Ardupilot on my own in the past and wondered if it would be helpful to move some of the stuff to an FPGA. It would be amazing if we could work together on this sort of thing!

I think maybe the first step is to get ardupilot working on a base circuit we build in DesignLab around the ZPUino. Do you have any recommended hardware that I should look into getting?

What do you think would benefit from moving it into hardware elements connected to the wishbone bus?

Jack.

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Hi Jack ,

I'm happy that you like this idea ... I already developed an Autopilot : VR Brain 5 that is the first board that support 32 bit processor i use STM32F4 . 

So i investigate some about the power of ZPuino it's similar to AVR x 6 ... Actually STM32F4 is like AVR x 22 the main difference is that on STM32F4 there is a math co processor. 

So for develop a good autopilot we need 2-3 serial port 1 or 2  SPI BUS 1 i2C BUS .

Actually we use as sensor MPU6500 (SPI) , MSIC Barometer (SPI ) HMC5883 (i2C) GPS ( 1 Serial Port )  Telm1 and Telm2 (serial Port) 

As dev tool we use Eclipse the 32 bit version of code is near 700 kbyte on flash the 8 bit version is 250 kbyte . ATMEGA 2560 . 

The actual version of Ardupilot have a Hardware Abstraction Layer where is implemented the driver for interface the hardware in low level with OS or without OS . So the main work could be write the HAL interface for ZPUINO without OS ... Actually we use on STM32F4 nuttx os . 

Why develop on FPGA with a softcore ? Because it's cool :) And so we could have a indipendent hard core cpu autopilot ... 

We intend to investigate also about the use of zinq or other fpga for : IQ RF Modulator , Video Stabilization , DVB-T modulator , Stereo Camera , H264/5 compressor and a lot of cool functionality for robotic application :)

This is our repo : https://github.com/virtualrobotix

I don't have so much experience on VHDL programming and don't know the limit of FPGA so what do you think about the different option that i explain in my post ? 

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If you want to discuss live about the specification and requirment of an APM system my skype account is : virtualrobotix  

best

Roberto 

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