virtualrobotix

Problem with DCM and FM SOS Example with Papilio DUO

7 posts in this topic

Dear Friends,

i'm very happy to Papilio DUO board. I try the SDK software on windows 10 but don't work , with Linux ubuntu instead all work fine. 

So now i try ISE and compile this code :

https://en.wikiversity.org/wiki/Papilio_FM_transmitter 

I have some problem during compiling i have this error : 

ERROR:NgdBuild:604 - logical block 'fast_clock' with type 'clocking' could not
   be resolved. A pin name misspelling can cause this, a missing edif or ngc
   file, case mismatch between the block name and the edif or ngc file name, or
   the misspelling of a type name. Symbol 'clocking' is not supported in target
   'spartan6'.

Can you help me to understand how solve the problem ? 

I try to found DCM with Spartan6 it isn't supported. So i don't know how solve the iusse on the code .

best

Roberto Navoni

 

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Hi,

Hamster's original project was done on the same FPGA you're using (XC6LX9) so all the hardware should be there.
Looking at this code I suspect you have to create the "clocking" component as an IP block (in other words, this part is not included in the shown code):

- In ISE, select "Tools" then "Core generator" in the menu (note: the available selections may vary, depending on where you are in your project)
- Go to "FPGA features", "clocking", "clocking wizard".
- set input frequency to 32 MHz, output frequency to 320 MHz, turn off optional inputs
- set the expected name

--------------------------------------------------------------------------------------------------------

As a general comment: It is all too common to end up in a situation "it doesn't work and I have no clue why".
You've picked quite a challenging project, because it'll give you no hints whatsoever why it doesn't work.

A better plan could be:

- create a trivial three-line design where you route the 32 MHz input clock to the LED (thirty lines in VHDL :) )
Sounds dull but most likely you'll encounter and solve 90 % of all the problems in this step. When done, the LED should glow steadily.
If in doubt, look at it the other way around: If I can't make the LED glow, do I really believe I am ready to handle a FM transmitter...
- implement a 24-bit counter on the input clock (32 MHz) and route the MSB to the LED. It should blink at 1 Hz or so. Confirm that it works
- implement the 32-MHz to 320 MHz clocking block and drive the same counter from it. Verify that it blinks at 10 Hz (if in doubt, move the board around quickly and you'll see that it blinks)
- once you've confirmed the counter, add the rest of the code.

This is at least how I'd approach it.
You might have a look at Hamster's VHDL material for an easier start. Why jump in at the deep end:

http://hamsterworks.co.nz/mediawiki/index.php/FPGA_course

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Hi offroard,

thanks very much for your reply ... and link to course . I'm a new with VHDL so i have some limit and need study :)

The main problem that i was is on DCM IP that is not available for Spartan 6 and so cannot follow the tutorial now try how i can write a work around. 

Best

Roberto .

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Hi,

did you notice that the Spartan 3 project you're trying to convert to Spartan 6 has been originally converted from a Spartan 6 project? See the link...

"DCM" is just another word for this:

>> - In ISE, select "Tools" then "Core generator" in the menu (note: the available selections may vary, depending on where you are in your project)
>> - Go to "FPGA features", "clocking", "clocking wizard".

a.pngc.png

 

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Maybe one more comment, taking a step up:

What we've got here is a fundamental FPGA design concept: The FPGA provides a mind-boggling supply of generic logic operations like "nand", "nor", etc.
In addition, you get quite a number of ready-made, specialized hardware blocks. The "DCM" you are asking for is an example:
The XC6LX9 comprises two "clock management tiles" aka "CMT". Each "CMT" contains "two DCMs and one PLL". I know this from footnote [5] on page 2 of the datasheet.

And this block will take a clock signal at some known frequency and transform it (by fair means or foul) into another frequency.

Part of the fun with FPGAs is knowing your hardware, what it can do.

For example, the Xilinx chip on your board provides

- dual-port Block rams (completely independent read-/ write access through two interfaces)
- Multipliers / accumulators for number crunching
- digital IO pins with supporting magic like serialize/deserialize
- ...

and you can take them and connect them as you like.

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Hi offroad ,

thanks for your reply ... today i try other sample that i found around the network ...

Quote

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity morse is
    Port ( CLK        : in  STD_LOGIC;
           Arduino_0  : in  STD_LOGIC;
           Arduino_1  : out STD_LOGIC;
           Arduino_2 : out STD_LOGIC_VECTOR (3 downto 0));
end morse;

architecture Behavioral of morse is
    signal carrier_counter : unsigned( 9 downto 0) := to_unsigned(0,10);
    signal tone_counter    : unsigned(16 downto 0) := to_unsigned(0,17);
    signal carrier         : std_logic := '0';
    signal tone            : std_logic := '0';
begin

process(CLK)
    begin
        if rising_edge(CLK) then
           Arduino_1 <= Arduino_0;
           -- Do we output the 50% level, or the modulated levels? 
           if Arduino_0 = '0' then
                 Arduino_2 <= carrier & '0' & carrier & '0';
           else
                if tone = '1' then
                    Arduino_2 <= carrier & carrier & carrier & '0';
                else
                    Arduino_2 <= '0' & carrier & '0' & '0';
                end if;
           end if;
           
           -- Update the counters for the carrier and modulation tone
           if carrier_counter = (100_000_000/2_000_000)-1 then
                carrier_counter <= to_unsigned(0, carrier_counter'length);
                carrier <= not carrier;
           else
                carrier_counter <= carrier_counter + 1;
           end if;

           if tone_counter = 100_000_000/880-1 then
                tone_counter <= to_unsigned(0,tone_counter'length);
                tone <= not tone;
           else
                tone_counter <= tone_counter + 1;
           end if;
        end if;
    end process;

end Behavioral;

With this code i change the name of variable with the description that i found in papilio_duo ucf file ... 

I don't know exactly if is possible assign a variable like arduino_0 port  to another name like LED0 . Is possible to mantain the same .ucf and assign the LED0 <= Arudino_0 or is a wrong syntax or is possilbe ? 

The variable assigned at phisical pin are global in VHDL code ? or is as in 'c' languange that exist local and global variable ? 

I used that definition in the .udf for assign Phisical pin in right position : 


NET CLK      LOC="P94"  | IOSTANDARD=LVTTL;                                                       # CLK
TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%;
NET TXD       LOC="P141" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;                                                  # TX
NET RXD       LOC="P46" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;                                                     # RX

NET Arduino_0          LOC="P116" | IOSTANDARD=LVTTL;                                # A0
NET Arduino_1          LOC="P117" | IOSTANDARD=LVTTL;                                # A1
NET Arduino_2          LOC="P118" | IOSTANDARD=LVTTL;                                # A2

 

I compiled the code and obtain morse.bit file so i think that i did a step forward .. and i'm ready to test the program to FPGA :) Now the only doubt is about the frequency set on trasmitter with actual clock setting. 

For change the periood i think that i to change the  TIMESPEC definition .. to value that corrispond to frequency that i would use for my modulator is correct ? 

Best

Roberto 

 

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2 hours ago, offroad said:

Hi,

did you notice that the Spartan 3 project you're trying to convert to Spartan 6 has been originally converted from a Spartan 6 project? See the link...

"DCM" is just another word for this:

>> - In ISE, select "Tools" then "Core generator" in the menu (note: the available selections may vary, depending on where you are in your project)
>> - Go to "FPGA features", "clocking", "clocking wizard".

a.pngc.png

 

In my previous test i already done this step but the result of new IP was quite different respect simple dcm in the description ... but after read the course i confident about apply right change to the code for my great PAPILIO DUO board :)

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