Working on Papilio Nano


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Hey Everyone,

I just wanted to make an official thread about a new project I'm working on, the Papilio Nano. 

Here is some info from another thread:

Going to use the Spartan 6 LX9 TQFP 144 for this since it is the cheapest and most readily available chip on the market.

This board has 32 pins available on the Wing headers, 8-12 are reserved for USB, and the remainder go to the high speed Mini PCI Express connector for things like memory, high speed ADC, high speed USB etc.

My goal with this board is to get the price way, way down. To the point where it would be a no brainer to throw this in a project and forget about it, like the Arduino. Everything I've done in this design is meant to cut costs:

  • I eliminated the costly FT2232D chip and replaced with a low cost USB transceiver. We go from $3-5 to $.60
  • Some projects need memory and others are just fine eliminating that expense. For maximum flexibility I will not include external memory but will allow people to add it if they need it using the Mini PCIe connector. SDRAM costs $3-5 and the connector should be around $.15-.60

Until I get a quote from a manufacturer I won't know the final price, but I'm hoping I can sell these for less then $30.

And here are some pictures:

20160606_101657.jpg20160606_101753.jpg20160606_101705.jpg20160606_101716.jpg20160606_101732.jpg

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This little guy will use the work that Alvie has done with the USB Transceiver Wing to get the cost way down and do some cool tricks like loading a bit file by dragging and dropping it on to a drive mapped on your computer. :)

I just ordered all the parts and will keep you posted about the progress.

Jack.

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On 6/12/2016 at 3:36 AM, shahabamo said:

great work!
Can it be used along with xilinx tools (like papilio-due)?

did you check the price with the manufactures? I am very eager to hear more about manufacturing steps involved in such a project.

 

Yes, it will work with all existing tools.

I haven't talked to my manufacturers yet to get quotes. I usually wait for a design to be completed before doing that... In this case I might talk to them sooner to try to find the most cost effective path.

Jack.

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Jack,

Do you use automatic assembly for your boards or house-assembly?
And just as a suggestion: Wouldn't it be better if you length-match all IO pins to each other? It may be possible that someone wants to design a high-speed peripheral (e.g. HDMI wing) for papilio nano in the future and it comes handy then.

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1 hour ago, shahabamo said:

Jack,

Do you use automatic assembly for your boards or house-assembly?
And just as a suggestion: Wouldn't it be better if you length-match all IO pins to each other? It may be possible that someone wants to design a high-speed peripheral (e.g. HDMI wing) for papilio nano in the future and it comes handy then.

I built this board by hand on a pancake griddle.

Good idea for length matching the IO pins. Right now these are just prototypes, I know that there will be at least one more revision before its ready for production so there is still time for time consuming additions like that at the end. If I have to rip up and re-route because I have to move a header - which it looks like I will have to do, then it was wasted effort that will have to be done over again. Right now I'm more concerned with whether the mini pcie connector and USB Transceiver are going to work out. But I like the idea of length matching the IO pins and trying to route diff pairs in the final design.

Cheers,

Jack.

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  • 2 months later...

Cool!

I hope the USB access to the design remains manageable. But it's maybe not the highest priority when the board can run without PC connection.
Question is, would I stick with FTDI and make USB a tightly integrated breakout board that can be omitted when the design runs off flash (an angled connector for JTAG, possibly to the backside).
I once bought a non-FTDI board (Xess Xula). The size is great but USB just didn't work for me. I use it only with an external JTAG+USB FTDI chip-in-a-box.
The lesson here is (note to self): double-check whether the PC-design interface really works. For the stuff I'm doing, RTL is business-as-usual (you get exactly the same as in the simulator) but the real complexity is in the driver, PC interface etc.

 

BTW, one cool and cheap feature is selectable IO voltage for an IO bank or two. It just needs some pads large enough to connect a wire e.g. to the 1.8 V regulator, and an exposed trace I can cut.
There aren't too many boards out there who can do this. Level shifters work only up to a point.

 

One user LED is IMHO absolutely essential.
Anyway, just some thoughts.

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FTDI is expensive. USB does not work for you because there are some implementation issues (note that there's a PIC controlling the USB). Also, lack of serial support on USB is a killer (I spoke with Dave a few years ago about that, but I also had no time to implement the new endpoint).

I have a few XuLa myself. I like them for some projects, due to the small size.

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Yea I didn't go into the details. Actually Dave was very helpful answering my questions but I realized I couldn't manage the installation on customer side PCs (it came down to a gut feeling "this won't work").
The Xula USB-via-JTAG idea is actually quite clever - why not make the unused pins work - but the volume I'm targeting didn't justify the effort, not by a factor of at least 100.

 

BTW for the Nano I'm just wondering whether a SRAM extension board would be possible.

A single 8MBit chip (256k x 8) e.g. IS61WV25616 provides as much memory as a much larger FPGA in block RAM.
The access is a bit slower but predictably so (which turns working with SDRAM into such a mess)

It takes about 40 IOs. At first glance, the PCIe connector seems to have enough pads, but I don't know how many are ground.

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I think Jack thought about that SRAM usecase. :)

Regarding USB:

Our plan for USB is to have a "master bitfile" that, when invoked, presents a MTD device to the host for programming (drag-drop a bitfile). Works in all OS without any drivers. Plus a CDC serial port for debugging or serial programming.

After the user bitfile starts, the USB PHY is completely available to the user to do whatever he wants (like a videocamera, for example). Or you can just power it down.

Alvie

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Hey everyone,

I went away on a week long roadtrip to visit my sister in beautiful Bellingham, Washington so I have been out of the loop for a couple days here. But I should be getting back tomorrow and back to the office on Wednesday. Before I left I had just finished putting together a couple of the first Nano sample boards and should be testing them out and posting pictures as soon as I get back. They look really cool and I'm excited to get some into Alvie's hands and start putting them through their paces! 

The newer version that I made uses a PHY that will be capable of 480 Mb/s but the downside is that there is no way to reset it if there is not a USB core already running on the FPGA. In that scenario people will have to hit the reset button. I'm very curious to hear if that is a deal breaker in people's opinion or if the low cost and highly flexible 480 Mb/s capability trumps that issue?

More to come as soon as I get back to the office.

Jack.

 

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On 8/18/2016 at 11:56 AM, offroad said:

Yea I didn't go into the details. Actually Dave was very helpful answering my questions but I realized I couldn't manage the installation on customer side PCs (it came down to a gut feeling "this won't work").
The Xula USB-via-JTAG idea is actually quite clever - why not make the unused pins work - but the volume I'm targeting didn't justify the effort, not by a factor of at least 100.

 

BTW for the Nano I'm just wondering whether a SRAM extension board would be possible.

A single 8MBit chip (256k x 8) e.g. IS61WV25616 provides as much memory as a much larger FPGA in block RAM.
The access is a bit slower but predictably so (which turns working with SDRAM into such a mess)

It takes about 40 IOs. At first glance, the PCIe connector seems to have enough pads, but I don't know how many are ground.

Yes, the intention in using the PCIe connector is to enable connecting several different daughterboards such as SRAM, SDRAM, DDR, or even high speed devices such as an ADC or a high speed USB device such as the Cypress USB chips. I'm not acutally following the PCIe pinout, I'm using the PCIe connector because it is cheap and readily available on the Chinese market but am using my own pinout that uses as many free FPGA pins as possible. Don't remember off the top of my head how many I put on there but it was enough for SDRAM or SRAM interfaces.

Jack.

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Ok, so I just finished soldering all of the Papilio Nano boards up and tested them for a valid power supply. I'm actually changing the name from Papilio Nano to Papilio Mini because I think I can make an even smaller board if I use a BGA chip so I want to reserve Nano for that board. 

There are three revisions that I have made, each is a little different size and different features. Here are all three to compare size:

20160825_115328.jpg

Version 1.0 is the smallest possible size, it uses the slower USB 1.0 PHY chip and has 32 I/O pins:

20160825_115351.jpg

Version 1.3.1 is slightly bigger in order to add GND, 3.3V, and 5V pins to the top and bottom of the Wing Headers. This is so it can be plugged into a breadboard. This uses the faster USB3300 PHY.

20160825_115408.jpg

Version 1.4 is the biggest board (I think it is too big...) but it provides 40 I/O pins and GND, 3.3V, and 5V in breadboard friendly pins. It also uses the faster USB3300 PHY:

20160825_115417.jpg

20160825_115425.jpg

This is what it looks like with SDRAM plugged into the PCIe connector:

20160825_115623.jpg

I would love some feedback about the sizes and how important the 40 I/O pins are vs the more compact size with 32 I/O pins.

Jack. 

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Yahoo, I connected to all boards over the JTAG port and did a successful IDCODE loop test. This test reads the device IDCODE 10,000 times and each board passed perfectly. When a new board passes this test I don't usually have any problems with it being stable.

Hmmm, what to test next. I want to load a bitfile, but which one....

Jack.

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Hi Jack,

for me, the images aren't loading (" Version 1.3.1" onwards). There is only a grey one-way street sign (Mozilla), or two consecutive lines with random characters (Tor browser).
The other images in the thread work fine. Might be a problem with my computer, though.

I think most GPIOs are used for extension boards with a high IO count, and the PCIe-style connector should take care of that. If the board mainly targets a small size, I'd consider making that a priority (but that's just a thought, not much of an opinion).

-------------------
BTW, I'd love to see a quality audio codec plugin.
I can think of one use case for a small board with minimum IO and audio: Guitar speaker (cabinet) simulator with a convolutional reverb. For example, the one in the Line6 Helix hi-end pedal needs only a 2048 point impulse response. The XC6LX9 can brute-force this using only a single DSP48 block for MAC and 2 x 2k/18 bit block RAMs for delay line + coefficients (e.g. 100 MHz clock => 2000 clock cycles per 48k audio sample).



 

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